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[Qemu-devel] [PULL 01/28] hw/intc/arm_gicv3: fix an extra left-shift whe
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/28] hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR |
Date: |
Fri, 22 Jun 2018 13:56:46 +0100 |
From: Amol Surati <address@hidden>
When either GICD_IPRIORITYR or GICR_IPRIORITYR is read as a 32-bit
register, the post left-shift operator in the for loop causes an
extra shift after the least significant byte has been placed.
The 32-bit value actually returned is therefore the expected value
shifted left by 8 bits.
Signed-off-by: Amol Surati <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_dist.c | 3 ++-
hw/intc/arm_gicv3_redist.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 93fe936862a..53c55c57291 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -441,7 +441,8 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
int i, irq = offset - GICD_IPRIORITYR;
uint32_t value = 0;
- for (i = irq + 3; i >= irq; i--, value <<= 8) {
+ for (i = irq + 3; i >= irq; i--) {
+ value <<= 8;
value |= gicd_read_ipriorityr(s, attrs, i);
}
*data = value;
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8a8684d76ed..3b0ba6de1ab 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -192,7 +192,8 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr
offset,
int i, irq = offset - GICR_IPRIORITYR;
uint32_t value = 0;
- for (i = irq + 3; i >= irq; i--, value <<= 8) {
+ for (i = irq + 3; i >= irq; i--) {
+ value <<= 8;
value |= gicr_read_ipriorityr(cs, attrs, i);
}
*data = value;
--
2.17.1
- [Qemu-devel] [PULL 05/28] target/arm: Allow KVM device address overwriting, (continued)
- [Qemu-devel] [PULL 05/28] target/arm: Allow KVM device address overwriting, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 18/28] hw/misc/tz-mpc.c: Implement registers, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 20/28] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 25/28] target/arm: Introduce ARM_FEATURE_M_MAIN, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 15/28] target-arm: Add the Cortex-R5F, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 16/28] xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 03/28] target-arm: fix a segmentation fault due to illegal memory access, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 06/28] hw/intc/arm_gicv3: Introduce redist-region-count array property, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 19/28] hw/misc/tz-mpc.c: Implement correct blocked-access behaviour, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 02/28] target/arm: Minor cleanup for ARMv6-M 32-bit instructions, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 01/28] hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR,
Peter Maydell <=
- [Qemu-devel] [PULL 21/28] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 17/28] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 22/28] hw/arm/iotkit: Instantiate MPC, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 23/28] hw/arm/iotkit: Wire up MPC interrupt lines, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 26/28] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 27/28] vl.c: Don't zero-initialize statics for serial_hds, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 28/28] xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom(), Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 24/28] hw/arm/mps2-tz.c: Instantiate MPCs, Peter Maydell, 2018/06/22
- Re: [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2018/06/22