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[Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst()
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst() |
Date: |
Wed, 20 Jun 2018 13:05:58 +0100 |
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/translate.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 60d9287..a581330 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t
opc, int rt,
/* Load and store */
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
- int base, int16_t offset)
+ TCGv t0)
{
- TCGv t0 = tcg_temp_new();
-
- gen_base_offset_addr(ctx, t0, base, offset);
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
@@ -2480,15 +2477,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
default:
MIPS_INVAL("flt_ldst");
generate_exception_end(ctx, EXCP_RI);
- goto out;
+ break;
}
- out:
- tcg_temp_free(t0);
}
static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
int rs, int16_t imm)
{
+ TCGv t0 = tcg_temp_new();
+
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
switch (op) {
@@ -2497,11 +2494,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t
op, int rt,
check_insn(ctx, ISA_MIPS2);
/* Fallthrough */
default:
- gen_flt_ldst(ctx, op, rt, rs, imm);
+ gen_base_offset_addr(ctx, t0, rs, imm);
+ gen_flt_ldst(ctx, op, rt, t0);
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
+ tcg_temp_free(t0);
}
/* Arithmetic with immediate operand */
--
1.9.1
- [Qemu-devel] [PATCH 07/35] target/mips: Add nanoMIPS save and restore, (continued)
- [Qemu-devel] [PATCH 07/35] target/mips: Add nanoMIPS save and restore, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 08/35] target/mips: Add nanoMIPS 32bit instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 09/35] target/mips: Add nanoMIPS 48bit instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 10/35] target/mips: Add nanoMIPS pool32f instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 11/35] target/mips: Add nanoMIPS pool32a0 instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 12/35] target/mips: Add nanoMIPS pool32axf instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst(),
Yongbok Kim <=
- [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 15/35] target/mips: Implement nanoMIPS EXTW instruction, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair, Yongbok Kim, 2018/06/20