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Re: [Qemu-devel] [PATCH] hw/pci-host/xilinx-pcie: don't make "io" region
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH] hw/pci-host/xilinx-pcie: don't make "io" region be RAM |
Date: |
Tue, 19 Jun 2018 11:48:25 -0700 |
On Tue, Jun 19, 2018 at 5:07 AM, Peter Maydell <address@hidden> wrote:
> Currently we use memory_region_init_rom_nomigrate() to create
> the "io" memory region to pass to pci_register_root_bus().
> This is a dummy region, because this PCI controller doesn't
> support accesses to PCI IO space.
>
> There is no reason for the dummy region to be a RAM region;
> it is only used as a place where PCI BARs can be mapped,
> and if you could get a PCI card to do a bus master access
> to the IO space it should not get acts-like-RAM behaviour.
> Use a simple container memory region instead. (We do have
> one PCI card model which can do bus master accesses to IO
> space -- the LSI53C895A SCSI adaptor.)
>
> This avoids the oddity of having a memory region which is
> RAM but where the RAM is not migrated.
>
> Note that the size of the region we use here has no
> effect on behaviour.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/pci-host/xilinx-pcie.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c
> index 044e312dc18..b0a31b917d8 100644
> --- a/hw/pci-host/xilinx-pcie.c
> +++ b/hw/pci-host/xilinx-pcie.c
> @@ -120,9 +120,8 @@ static void xilinx_pcie_host_realize(DeviceState *dev,
> Error **errp)
> memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
> memory_region_set_enabled(&s->mmio, false);
>
> - /* dummy I/O region */
> - memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);
> - memory_region_set_enabled(&s->io, false);
> + /* dummy PCI I/O region (not visible to the CPU) */
> + memory_region_init(&s->io, OBJECT(s), "io", 16);
>
> /* interrupt out */
> qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
> --
> 2.17.1
>
>