Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

[Konrad Rzeszutek Wilk]

On Mon, Jun 04, 2018 at 09:54:40AM +0100, Daniel P. Berrangé wrote:
> On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote:
> > AMD future CPUs expose _two_ ways to utilize the Intel equivalant
> > of the Speculative Store Bypass Disable. The first is via
> > the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
> > is via the SPEC_CTRL MSR (0x48). The document titled:
> > 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> > 
> > gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
> > 
> > A copy of this document is available at
> >       https://bugzilla.kernel.org/show_bug.cgi?id=199889
> > 
> > Anyhow, this means that on future AMD CPUs there will be  _two_ ways to
> > deal with SSBD.
> 
> Oh what fun ;-)
> 
> Unless I'm mistaken the current Linux kernel doesn't know about these
> new amd-ssbd / amd-no-ssb flags either. Will you also be sending patches
> for that half of the problem ?

I sent them as well. But forgot to CC qemu-devel :-(