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Re: [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support |
Date: |
Fri, 25 May 2018 11:53:27 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/22/2018 05:15 PM, Michael Clark wrote:
> + /* Suppress 'C' if next instruction is not aligned
> + TODO: this should check next_pc */
> + if ((val & RVC) && (GETPC() & ~3) != 0) {
> + val &= ~RVC;
> + }
This is checking the host PC, which is useless.
Isn't this backward anyway? Why would *setting* C require an aligned address?
Surely it's *clearing* C that would require an aligned address.
You can read the guest PC of the current instruction by doing
cpu_restore_state(cs, GETPC(), false);
xxx = env->pc;
In order to get the next pc, I guess you'd just need to add 4, since all of the
csr insns are not in the compact encoding space?
Alternately, to save the not insignificant amount of work that
cpu_restore_state does, and since all of the csr insns end the TB anyway, you
could move
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
before the call to helper_csr*. If an exception is raised by the helper, this
store to PC will be overwritten by the existing cpu_restore_state in
do_raise_exception_err so that the correct PC value is seen on entry to
do_interrupt.
r~
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, (continued)
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, Michael Clark, 2018/05/22
- Re: [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support,
Richard Henderson <=
- [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines, Michael Clark, 2018/05/22