[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper |
Date: |
Wed, 23 May 2018 09:23:58 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/22/2018 09:14 PM, Michael Clark wrote:
> This patch makes op_helper.c contain only instruction
> operation helpers used by translate.c and moves any
> unrelated cpu helpers into cpu_helper.c. No logic is
> changed by this patch.
>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/riscv/Makefile.objs | 2 +-
> target/riscv/{helper.c => cpu_helper.c} | 35
> ++++++++++++++++++++++++++++++++-
> target/riscv/op_helper.c | 34 --------------------------------
> 3 files changed, 35 insertions(+), 36 deletions(-)
> rename target/riscv/{helper.c => cpu_helper.c} (95%)
>
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index abd0a7cde333..fcc5d34c1f2e 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1 +1 @@
> -obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
> +obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o
> pmp.o
> diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c
> similarity index 95%
> rename from target/riscv/helper.c
> rename to target/riscv/cpu_helper.c
> index 47d116e9c13f..6c886e99055a 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V emulation helpers for qemu.
> + * RISC-V CPU helpers for qemu.
> *
> * Copyright (c) 2016-2017 Sagar Karandikar, address@hidden
> * Copyright (c) 2017-2018 SiFive, Inc.
> @@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
>
> #if !defined(CONFIG_USER_ONLY)
>
> +/* iothread_mutex must be held */
> +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> +{
> + CPURISCVState *env = &cpu->env;
> + uint32_t old, new, cmp = atomic_read(&env->mip);
> +
> + do {
> + old = cmp;
> + new = (old & ~mask) | (value & mask);
> + cmp = atomic_cmpxchg(&env->mip, old, new);
> + } while (old != cmp);
> +
> + if (new && !old) {
> + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + } else if (!new && old) {
> + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + }
> +
> + return old;
> +}
> +
> +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +{
> + if (newpriv > PRV_M) {
> + g_assert_not_reached();
> + }
> + if (newpriv == PRV_H) {
> + newpriv = PRV_U;
> + }
> + /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> + env->priv = newpriv;
> +}
> +
> /* get_physical_address - get the physical address for this virtual address
> *
> * Do a page table walk to obtain the physical address corresponding to a
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 5a02795bf931..2b9dd9da6486 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -652,39 +652,6 @@ target_ulong helper_csrrc(CPURISCVState *env,
> target_ulong src,
>
> #ifndef CONFIG_USER_ONLY
>
> -/* iothread_mutex must be held */
> -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> -{
> - CPURISCVState *env = &cpu->env;
> - uint32_t old, new, cmp = atomic_read(&env->mip);
> -
> - do {
> - old = cmp;
> - new = (old & ~mask) | (value & mask);
> - cmp = atomic_cmpxchg(&env->mip, old, new);
> - } while (old != cmp);
> -
> - if (new && !old) {
> - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - } else if (!new && old) {
> - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - }
> -
> - return old;
> -}
> -
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> -{
> - if (newpriv > PRV_M) {
> - g_assert_not_reached();
> - }
> - if (newpriv == PRV_H) {
> - newpriv = PRV_U;
> - }
> - /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> - env->priv = newpriv;
> -}
> -
> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_S)) {
> @@ -735,7 +702,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
> cpu_pc_deb)
> return retpc;
> }
>
> -
> void helper_wfi(CPURISCVState *env)
> {
> CPUState *cs = CPU(riscv_env_get_cpu(env));
>
- [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance, (continued)
- [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/05/22