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[Qemu-devel] [PATCH v3 17/38] target-microblaze: dec_msr: Use bool and e
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v3 17/38] target-microblaze: dec_msr: Use bool and extract32 |
Date: |
Wed, 16 May 2018 20:51:25 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Use bool and extract32 to represent the to, clr and
clrset flags.
No functional change.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b0a76fb23b..f623617fa0 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -458,17 +458,20 @@ static void dec_msr(DisasContext *dc)
{
CPUState *cs = CPU(dc->cpu);
TCGv_i32 t0, t1;
- unsigned int sr, to, rn;
+ unsigned int sr, rn;
+ bool to, clrset;
- sr = dc->imm & ((1 << 14) - 1);
- to = dc->imm & (1 << 14);
+ sr = extract32(dc->imm, 0, 14);
+ to = extract32(dc->imm, 14, 1);
+ clrset = extract32(dc->imm, 15, 1) == 0;
dc->type_b = 1;
- if (to)
+ if (to) {
dc->cpustate_changed = 1;
+ }
/* msrclr and msrset. */
- if (!(dc->imm & (1 << 15))) {
- unsigned int clr = dc->ir & (1 << 16);
+ if (clrset) {
+ bool clr = extract32(dc->ir, 16, 1);
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
dc->rd, dc->imm);
--
2.14.1
- [Qemu-devel] [PATCH v3 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, (continued)
- [Qemu-devel] [PATCH v3 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 13/38] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 12/38] target-microblaze: Remove pointer indirection for ld/st addresses, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 14/38] target-microblaze: Name special registers we support, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 15/38] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 16/38] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 18/38] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 19/38] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 17/38] target-microblaze: dec_msr: Use bool and extract32,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v3 20/38] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 23/38] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 21/38] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 25/38] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 26/38] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/16
- [Qemu-devel] [PATCH v3 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/16