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[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg |
Date: |
Tue, 15 May 2018 15:06:59 +0100 |
From: Richard Henderson <address@hidden>
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d0ed125442..78f12daaf6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -615,6 +615,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
return v;
}
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
+{
+ TCGv_i32 v = tcg_temp_new_i32();
+
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
+ return v;
+}
+
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
* If SVE is not enabled, then there are only 128 bits in the vector.
*/
@@ -4881,11 +4889,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{
TCGv_ptr fpst = NULL;
- TCGv_i32 tcg_op = tcg_temp_new_i32();
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
TCGv_i32 tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-
switch (opcode) {
case 0x0: /* FMOV */
tcg_gen_mov_i32(tcg_res, tcg_op);
@@ -7784,13 +7790,10 @@ static void
disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_op2);
tcg_temp_free_i64(tcg_res);
} else {
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
TCGv_i64 tcg_res = tcg_temp_new_i64();
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
-
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
@@ -8331,13 +8334,10 @@ static void
disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
fpst = get_fpstatus_ptr(true);
- tcg_op1 = tcg_temp_new_i32();
- tcg_op2 = tcg_temp_new_i32();
+ tcg_op1 = read_fp_hreg(s, rn);
+ tcg_op2 = read_fp_hreg(s, rm);
tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
-
switch (fpopcode) {
case 0x03: /* FMULX */
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
@@ -12235,11 +12235,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
}
if (is_scalar) {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
TCGv_i32 tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-
switch (fpop) {
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
--
2.17.0
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg,
Peter Maydell <=
- [Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch(), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising, Peter Maydell, 2018/05/15
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/05/15