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[Qemu-devel] [PATCH v3 01/11] target/arm: Implement FMOV (general) for f
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 01/11] target/arm: Implement FMOV (general) for fp16 |
Date: |
Thu, 10 May 2018 19:44:44 -0700 |
Adding the fp16 moves to/from general registers.
Cc: address@hidden
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b0471c842e..10d3856351 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5700,6 +5700,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn,
int type, bool itof)
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
clear_vec_high(s, true, rd);
break;
+ case 3:
+ /* 16 bit */
+ tmp = tcg_temp_new_i64();
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
+ write_fp_dreg(s, rd, tmp);
+ tcg_temp_free_i64(tmp);
+ break;
+ default:
+ g_assert_not_reached();
}
} else {
TCGv_i64 tcg_rd = cpu_reg(s, rd);
@@ -5717,6 +5726,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn,
int type, bool itof)
/* 64 bits from top half */
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
break;
+ case 3:
+ /* 16 bit */
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
+ break;
+ default:
+ g_assert_not_reached();
}
}
}
@@ -5756,6 +5771,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t
insn)
case 0xa: /* 64 bit */
case 0xd: /* 64 bit to top half of quad */
break;
+ case 0x6: /* 16-bit float, 32-bit int */
+ case 0xe: /* 16-bit float, 64-bit int */
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ break;
+ }
+ /* fallthru */
default:
/* all other sf/type/rmode combinations are invalid */
unallocated_encoding(s);
--
2.17.0
- [Qemu-devel] [PATCH v3 00/11] target/arm: Fixups for ARM_FEATURE_V8_FP16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 01/11] target/arm: Implement FMOV (general) for fp16,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 04/11] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 03/11] target/arm: Implement FCVT (scalar, integer) for fp16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 05/11] target/arm: Introduce and use read_fp_hreg, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 02/11] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 06/11] target/arm: Implement FP data-processing (2 source) for fp16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 08/11] target/arm: Implement FCMP for fp16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 09/11] target/arm: Implement FCSEL for fp16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 11/11] target/arm: Fix sqrt_f16 exception raising, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 07/11] target/arm: Implement FP data-processing (3 source) for fp16, Richard Henderson, 2018/05/10
- [Qemu-devel] [PATCH v3 10/11] target/arm: Implement FMOV (immediate) for fp16, Richard Henderson, 2018/05/10