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[Qemu-devel] [PATCH v8 4/8] i386: Initialize cache information for EPYC
From: |
Babu Moger |
Subject: |
[Qemu-devel] [PATCH v8 4/8] i386: Initialize cache information for EPYC family processors |
Date: |
Thu, 10 May 2018 15:41:44 -0500 |
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
---
target/i386/cpu.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d97b290b08..b20b8691a7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1112,6 +1112,56 @@ struct X86CPUDefinition {
CPUCaches *cache_info;
};
+static CPUCaches epyc_cache_info = {
+ .l1d_cache = {
+ .type = DCACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .l1i_cache = {
+ .type = ICACHE,
+ .level = 1,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .partitions = 1,
+ .sets = 256,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .l2_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .size = 512 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 1024,
+ .lines_per_tag = 1,
+ },
+ .l3_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .size = 8 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 8192,
+ .lines_per_tag = 1,
+ .self_init = true,
+ .inclusive = true,
+ .complex_indexing = true,
+ },
+};
+
static X86CPUDefinition builtin_x86_defs[] = {
{
.name = "qemu64",
@@ -2306,6 +2356,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor",
+ .cache_info = &epyc_cache_info,
},
{
.name = "EPYC-IBPB",
@@ -2352,6 +2403,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor (with IBPB)",
+ .cache_info = &epyc_cache_info,
},
};
--
2.17.0
- [Qemu-devel] [PATCH v8 0/8] i386: Enable TOPOEXT to support hyperthreading on AMD CPU, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 2/8] i386: Add cache information in X86CPUDefinition, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 4/8] i386: Initialize cache information for EPYC family processors,
Babu Moger <=
- [Qemu-devel] [PATCH v8 7/8] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 5/8] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 6/8] i386: Add support for CPUID_8000_001E for AMD, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 1/8] i386: Helpers to encode cache information consistently, Babu Moger, 2018/05/10
- [Qemu-devel] [PATCH v8 3/8] i386: Add new property to control cache info, Babu Moger, 2018/05/10