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[Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirectio
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection |
Date: |
Sun, 6 May 2018 11:35:15 +1200 |
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
target/riscv/cpu.h | 1 -
5 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 22dc526713c2..6fa223818502 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename)
if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
+ 0, EM_RISCV, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5bb495ab9a6c..84afed4c3b0e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename)
if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
+ 0, EM_RISCV, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 44eab94e17ef..9e18c618bfbb 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename)
uint64_t kernel_entry, kernel_high;
if (load_elf_ram_sym(kernel_filename, NULL, NULL,
- &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
+ &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
NULL, true, htif_symbol_callback) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 88b9ad509315..7ef9ba26debc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename)
if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
+ 0, EM_RISCV, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 41e06ac0f91d..9871e6feb1de 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -34,7 +34,6 @@
#define TCG_GUEST_DEFAULT_MO 0
-#define ELF_MACHINE EM_RISCV
#define CPUArchState struct CPURISCVState
#include "qemu-common.h"
--
2.7.0
- [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values, (continued)
- [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection,
Michael Clark <=
- [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/05/05
- Re: [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates, Peter Maydell, 2018/05/08