Re: [Qemu-devel] [PATCH v1 20/29] target-microblaze: Make special registers 64-bit

[Edgar E. Iglesias]

On Thu, May 03, 2018 at 12:03:19PM -0700, Richard Henderson wrote:
> On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <address@hidden>
> > 
> > Extend special registers to 64-bits. This is in preparation for
> > MFSE/MTSE, moves to and from extended special registers.
> > 
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> 
> Reviewed-by: Richard Henderson <address@hidden>
> 
> > @@ -1124,13 +1125,13 @@ static inline void eval_cc(DisasContext *dc, 
> > unsigned int cc,
> >      }
> >  }
> >  
> > -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 
> > pc_false)
> > +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i64 
> > pc_false)
> >  {
> >      TCGLabel *l1 = gen_new_label();
> >      /* Conditional jmp.  */
> > -    tcg_gen_mov_i32(cpu_SR[SR_PC], pc_false);
> > +    tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false);
> >      tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1);
> > -    tcg_gen_mov_i32(cpu_SR[SR_PC], pc_true);
> > +    tcg_gen_extu_i32_i64(cpu_SR[SR_PC], pc_true);
> >      gen_set_label(l1);
> >  }
> 
> For future cleanup, this should use tcg_gen_movcond_i32.

Thanks, I've added a follow-up patch in v2 that cleans this up.

Cheers,
Edgar