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Re: [Qemu-devel] [PATCH v8 04/23] RISC-V Disassembler
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v8 04/23] RISC-V Disassembler |
Date: |
Fri, 27 Apr 2018 13:26:01 +0100 |
On 2 March 2018 at 13:51, Michael Clark <address@hidden> wrote:
> The RISC-V disassembler has no dependencies outside of the 'disas'
> directory so it can be applied independently. The majority of the
> disassembler is machine-generated from instruction set metadata:
>
> - https://github.com/michaeljclark/riscv-meta
> + case 5:
> + if (isa == rv128) {
> + op = rv_op_c_sqsp;
> + } else {
> + op = rv_op_c_fsdsp; break;
> + }
> + case 6: op = rv_op_c_swsp; break;
Coverity (CID1390575) points out that for the
case 5 / isa == rv128 codepath, we set op, and
then fall through into case 6 which overwrites it.
Is there a missing "break" statement here? (If the
fallthrough is deliberate it should be marked with a
/* fallthrough */ comment.)
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v8 04/23] RISC-V Disassembler,
Peter Maydell <=