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Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation upd
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From: |
Michael Clark |
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Subject: |
Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates |
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Date: |
Fri, 27 Apr 2018 17:00:52 +1200 |
On Fri, Apr 27, 2018 at 12:35 PM, Richard Henderson <
address@hidden> wrote:
> On 04/26/2018 08:22 AM, Alistair Francis wrote:
> > On Wed, Apr 25, 2018 at 7:01 PM Michael Clark <address@hidden> wrote:
> >> We can make a PR for the first 9 patches as they are already reviewed,
> >> however, the with this series is to gather review for the new baseline
> we
> >> have in the riscv repo.
> >
> > I think it is worth sending a PR for the first 9 patches. The current
> > master doesn't boot the sifive_u board and those patches will fix that.
> > That also helps create a smaller patch series which is easier to review.
>
> FYI, for patches that affect usability like this, you should also Cc:
> address@hidden in your pull request. That way they should be
> cherry-picked from master into the 2.12.1 release.
>
Ok I will. Thanks.
- [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty, (continued)
- [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 35/35] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/04/25