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[Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags |
Date: |
Thu, 26 Apr 2018 11:45:33 +1200 |
From: Richard Henderson <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3fed92d..6fb0014 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -270,8 +270,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState
*env,
target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
-#define TB_FLAGS_FP_ENABLE MSTATUS_FS
+#define TB_FLAGS_MMU_MASK 3
+#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -279,7 +279,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
#ifdef CONFIG_USER_ONLY
- *flags = TB_FLAGS_FP_ENABLE;
+ *flags = TB_FLAGS_MSTATUS_FS;
#else
*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c0e6a04..4180c42 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -43,7 +43,7 @@ typedef struct DisasContext {
target_ulong pc;
target_ulong next_pc;
uint32_t opcode;
- uint32_t flags;
+ uint32_t mstatus_fs;
uint32_t mem_idx;
int singlestep_enabled;
int bstate;
@@ -664,7 +664,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc,
int rd,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -694,7 +694,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc,
int rs1,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -985,7 +985,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
int rd,
{
TCGv t0 = NULL;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
goto do_illegal;
}
@@ -1863,8 +1863,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock
*tb)
ctx.tb = tb;
ctx.bstate = BS_NONE;
- ctx.flags = tb->flags;
ctx.mem_idx = tb->flags & TB_FLAGS_MMU_MASK;
+ ctx.mstatus_fs = tb->flags & TB_FLAGS_MSTATUS_FS;
ctx.frm = -1; /* unknown rounding mode */
num_insns = 0;
--
2.7.0
- Re: [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, (continued)
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags,
Michael Clark <=
- [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 35/35] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/04/25