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Re: [Qemu-devel] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesse
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses |
Date: |
Fri, 20 Apr 2018 11:17:36 +0100 |
On 17 April 2018 at 21:37, Aaron Lindsay <address@hidden> wrote:
> pmccntr_read and pmccntr_write contained duplicate code that was already
> being handled by pmccntr_sync. Consolidate the duplicated code into two
> functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to
> c15_ccnt in CPUARMState so that we can simultaneously save both the
> architectural register value and the last underlying cycle count - this
> ensure time isn't lost and will also allow us to access the 'old'
> architectural register value in order to detect overflows in later
> patches.
>
> Signed-off-by: Aaron Lindsay <address@hidden>
> ---
> target/arm/cpu.h | 28 ++++++++++-----
> target/arm/helper.c | 100
> ++++++++++++++++++++++++++++------------------------
> 2 files changed, 73 insertions(+), 55 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 19a0c03..04041db 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -454,10 +454,20 @@ typedef struct CPUARMState {
> uint64_t oslsr_el1; /* OS Lock Status */
> uint64_t mdcr_el2;
> uint64_t mdcr_el3;
> - /* If the counter is enabled, this stores the last time the counter
> - * was reset. Otherwise it stores the counter value
> + /* Stores the architectural value of the counter *the last time it
> was
> + * updated* by pmccntr_op_start. Accesses should always be surrounded
> + * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
> + * architecturally-corect value is being read/set.
> */
> uint64_t c15_ccnt;
> + /* Stores the delta between the architectural value and the
> underlying
> + * cycle count during normal operation. It is used to update c15_ccnt
> + * to be the correct architectural value before accesses. During
> + * accesses, c15_ccnt_delta contains the underlying count being used
> + * for the access, after which it reverts to the delta value in
> + * pmccntr_op_finish.
> + */
> + uint64_t c15_ccnt_delta;
So the key question here is: how does this work for VM migration?
thanks
-- PMM
- [Qemu-devel] [PATCH v4 00/21] More fully implement ARM PMUv3, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 02/21] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 06/21] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 07/21] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 11/21] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 10/21] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 14/21] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 18/21] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 13/21] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/04/17
- [Qemu-devel] [PATCH v4 17/21] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/04/17