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[Qemu-devel] [PATCH v3 22/41] hw/alpha: Use the BYTE-based definitions
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v3 22/41] hw/alpha: Use the BYTE-based definitions |
Date: |
Sun, 15 Apr 2018 20:42:48 -0300 |
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/alpha/typhoon.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 6a40869488..85fe072063 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -7,6 +7,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/hw.h"
@@ -812,8 +813,6 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq,
AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
{
- const uint64_t MB = 1024 * 1024;
- const uint64_t GB = 1024 * MB;
MemoryRegion *addr_space = get_system_memory();
DeviceState *dev;
TyphoonState *s;
@@ -854,30 +853,30 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus
**isa_bus,
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",
- 256*MB);
+ 256 * M_BYTE);
memory_region_add_subregion(addr_space, 0x80180000000ULL,
&s->pchip.region);
/* Cchip CSRs, 0x801.A000.0000, 256MB. */
memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",
- 256*MB);
+ 256 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801a0000000ULL,
&s->cchip.region);
/* Dchip CSRs, 0x801.B000.0000, 256MB. */
memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",
- 256*MB);
+ 256 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801b0000000ULL,
&s->dchip_region);
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
- memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB);
+ memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4 * G_BYTE);
memory_region_add_subregion(addr_space, 0x80000000000ULL,
&s->pchip.reg_mem);
/* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops,
- NULL, "pci0-io", 32*MB);
+ NULL, "pci0-io", 32 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io);
@@ -898,13 +897,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus
**isa_bus,
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops,
- b, "pci0-iack", 64*MB);
+ b, "pci0-iack", 64 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801f8000000ULL,
&s->pchip.reg_iack);
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops,
- b, "pci0-conf", 16*MB);
+ b, "pci0-conf", 16 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801fe000000ULL,
&s->pchip.reg_conf);
--
2.17.0
- [Qemu-devel] [PATCH v3 12/41] hw/tpm: Use the BYTE-based definitions, (continued)
- [Qemu-devel] [PATCH v3 12/41] hw/tpm: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 13/41] hw/block: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 15/41] hw/misc: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 16/41] hw/riscv: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 17/41] hw/m68k: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 18/41] hw/sparc: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 19/41] hw/s390x: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 20/41] hw/hppa: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 21/41] hw/xtensa: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 22/41] hw/alpha: Use the BYTE-based definitions,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v3 23/41] hw/tricore: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 24/41] hw/microblaze: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 25/41] hw/nios2: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 26/41] hw/cris: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 27/41] hw/lm32: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 28/41] hw/sh4: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 29/41] hw/mips: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15
- [Qemu-devel] [PATCH v3 30/41] hw/arm: Use the BYTE-based definitions, Philippe Mathieu-Daudé, 2018/04/15