Re: [Qemu-devel] [PATCH v2 00/23] RISC-V Post-merge spec conformance and cleanup

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v2 00/23] RISC-V Post-merge spec conformance and 
cleanup

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
 * [new tag]               patchew/address@hidden -> patchew/address@hidden
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
1a093fa312 RISC-V: Convert cpu definition towards future model
60f285ab8d RISC-V: Remove support for adhoc X_COP interrupt
533511fbfb RISC-V: No traps on writes to misa, minstret, mcycle
395b5ff5df RISC-V: vectored traps are optional
01f250ec13 RISC-V: riscv-qemu port supports sv39 and sv48
728a31f9ba RISC-V: Remove braces from satp case statement
1eea106c3d RISC-V: Hardwire satp to 0 for no-mmu case
6624b330f8 RISC-V: Remove EM_RISCV ELF_MACHINE indirection
0c41b7c63e RISC-V: Use memory_region_is_ram in pte update
31404ec043 RISC-V: Make virt header comment title consistent
8c2d250fd4 RISC-V: Make some header guards more specific
bca06d8667 RISC-V: Update E order and I extension order
311f569e1a RISC-V: Improve page table walker spec compliance
0e3a08f02f RISC-V: Hold rcu_read_lock when accessing memory
f4b56b6603 RISC-V: Include intruction hex in disassembly
252c5a7b3f RISC-V: Make sure rom has space for fdt
07c1f8bc05 RISC-V: Remove unused class definitions
b55bf136ea RISC-V: Mark ROM read-only after copying in code
68db62e5ae RISC-V: Remove identity_translate from load_elf
089c002a16 RISC-V: Use ROM base address and size from memmap
560b8e3327 RISC-V: Make virt board description match spike
e7af5f102c RISC-V: Replace hardcoded constants with enum values
9f5038bb7b RISC-V: Make virt create_fdt interface consistent

=== OUTPUT BEGIN ===
Checking PATCH 1/23: RISC-V: Make virt create_fdt interface consistent...
Checking PATCH 2/23: RISC-V: Replace hardcoded constants with enum values...
Checking PATCH 3/23: RISC-V: Make virt board description match spike...
Checking PATCH 4/23: RISC-V: Use ROM base address and size from memmap...
Checking PATCH 5/23: RISC-V: Remove identity_translate from load_elf...
Checking PATCH 6/23: RISC-V: Mark ROM read-only after copying in code...
Checking PATCH 7/23: RISC-V: Remove unused class definitions...
Checking PATCH 8/23: RISC-V: Make sure rom has space for fdt...
Checking PATCH 9/23: RISC-V: Include intruction hex in disassembly...
Checking PATCH 10/23: RISC-V: Hold rcu_read_lock when accessing memory...
Checking PATCH 11/23: RISC-V: Improve page table walker spec compliance...
Checking PATCH 12/23: RISC-V: Update E order and I extension order...
Checking PATCH 13/23: RISC-V: Make some header guards more specific...
Checking PATCH 14/23: RISC-V: Make virt header comment title consistent...
Checking PATCH 15/23: RISC-V: Use memory_region_is_ram in pte update...
Checking PATCH 16/23: RISC-V: Remove EM_RISCV ELF_MACHINE indirection...
Checking PATCH 17/23: RISC-V: Hardwire satp to 0 for no-mmu case...
Checking PATCH 18/23: RISC-V: Remove braces from satp case statement...
Checking PATCH 19/23: RISC-V: riscv-qemu port supports sv39 and sv48...
Checking PATCH 20/23: RISC-V: vectored traps are optional...
ERROR: trailing whitespace
#27: FILE: target/riscv/op_helper.c:265:
+        /* we do not support vectored traps for asynchrounous interrupts */ $

ERROR: trailing whitespace
#42: FILE: target/riscv/op_helper.c:286:
+        /* we do not support vectored traps for asynchrounous interrupts */ $

total: 2 errors, 0 warnings, 28 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 21/23: RISC-V: No traps on writes to misa, minstret, mcycle...
Checking PATCH 22/23: RISC-V: Remove support for adhoc X_COP interrupt...
Checking PATCH 23/23: RISC-V: Convert cpu definition towards future model...
=== OUTPUT END ===

Test command exited with code: 1


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