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Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission |
Date: |
Sat, 10 Mar 2018 04:07:21 +1300 |
On Mon, Mar 5, 2018 at 9:41 PM, Richard W.M. Jones <address@hidden>
wrote:
>
> The attached patch is also needed to avoid crashes during various
> math-heavy test suites.
>
Thanks. I missed your email.
I've integrated this and the other outstanding patches into the `riscv-all`
branch in the riscv repo here.
- https://github.com/riscv/riscv-qemu/commits/riscv-all
This also triggered aborts on riscv-tests, which is all the more reason to
get riscv-tests running in the CI so we spot these things early.
Thanks,
Michael.
Rich.
>
> From: Stef O'Rear <address@hidden>
>
> Date: Sat, 3 Mar 2018 03:46:00 -0800
>
> Subject: [PATCH] softfloat: fix crash on int conversion of SNaN
>
>
>> Signed-off-by: Stef O'Rear <address@hidden>
>
>
Signed-off-by: Michael Clark <address@hidden>
> ---
>
> fpu/softfloat.c | 4 ++++
>
> 1 file changed, 4 insertions(+)
>
>
>> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
>
> index e7fb0d357a..1da1db377e 100644
>
> --- a/fpu/softfloat.c
>
> +++ b/fpu/softfloat.c
>
> @@ -1342,6 +1342,8 @@ static int64_t round_to_int_and_pack(FloatParts in,
>> int rmode,
>
> switch (p.cls) {
>
> case float_class_snan:
>
> case float_class_qnan:
>
> + case float_class_dnan:
>
> + case float_class_msnan:
>
> return max;
>
> case float_class_inf:
>
> return p.sign ? min : max;
>
> @@ -1430,6 +1432,8 @@ static uint64_t round_to_uint_and_pack(FloatParts
>> in, int rmode, uint64_t max,
>
> switch (p.cls) {
>
> case float_class_snan:
>
> case float_class_qnan:
>
> + case float_class_dnan:
>
> + case float_class_msnan:
>
> s->float_exception_flags = orig_flags | float_flag_invalid;
>
> return max;
>
> case float_class_inf:
>
> --
>
> 2.15.1
>
>
>