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[Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset |
Date: |
Thu, 1 Mar 2018 11:23:22 +0000 |
From: Alistair Francis <address@hidden>
Ensure that the post write hook is called during reset. This allows us
to rely on the post write functions instead of having to call them from
the reset() function.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/register.h | 6 +++---
hw/core/register.c | 8 ++++++++
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/hw/register.h b/include/hw/register.h
index de2414e6b4..5796584588 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -34,7 +34,7 @@ typedef struct RegisterInfoArray RegisterInfoArray;
* immediately before the actual write. The returned value is what is written,
* giving the handler a chance to modify the written value.
* @post_write: Post write callback. Passed the written value. Most write side
- * effects should be implemented here.
+ * effects should be implemented here. This is called during device reset.
*
* @post_read: Post read callback. Passes the value that is about to be
returned
* for a read. The return value from this function is what is ultimately read,
@@ -135,8 +135,8 @@ uint64_t register_read(RegisterInfo *reg, uint64_t re,
const char* prefix,
bool debug);
/**
- * reset a register
- * @reg: register to reset
+ * Resets a register. This will also call the post_write hook if it exists.
+ * @reg: The register to reset.
*/
void register_reset(RegisterInfo *reg);
diff --git a/hw/core/register.c b/hw/core/register.c
index 900294b9c4..0741a1af32 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -159,13 +159,21 @@ uint64_t register_read(RegisterInfo *reg, uint64_t re,
const char* prefix,
void register_reset(RegisterInfo *reg)
{
+ const RegisterAccessInfo *ac;
+
g_assert(reg);
if (!reg->data || !reg->access) {
return;
}
+ ac = reg->access;
+
register_write_val(reg, reg->access->reset);
+
+ if (ac->post_write) {
+ ac->post_write(reg, reg->access->reset);
+ }
}
void register_init(RegisterInfo *reg)
--
2.16.2
- [Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, (continued)
- [Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset,
Peter Maydell <=
- [Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 41/42] linux-user: Report AArch64 FP16 support via hwcap bits, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 42/42] MAINTAINERS: Update my email address, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 37/42] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 39/42] arm/translate-a64: add all single op FP16 to handle_fp_1src_half, Peter Maydell, 2018/03/01