Re: [Qemu-devel] [Qemu-arm] [PATCH v2 16/67] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group

[Peter Maydell]

On 17 February 2018 at 18:22, Richard Henderson
<address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate-sve.c | 41 ++++++++++++++++++++++++++++++++++++++---
>  target/arm/sve.decode      | 13 +++++++++++++
>  2 files changed, 51 insertions(+), 3 deletions(-)

> @@ -254,7 +288,8 @@ static void do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, 
> gen_helper_gvec_4 *fn)
>  }
>
>  #define DO_ZPZZ(NAME, name) \
> -void trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) \
> +static void trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a,         \
> +                                uint32_t insn)                            \
>  {                                                                         \
>      static gen_helper_gvec_4 * const fns[4] = {                           \
>          gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h,   \
> @@ -286,7 +321,7 @@ DO_ZPZZ(ASR, asr)
>  DO_ZPZZ(LSR, lsr)
>  DO_ZPZZ(LSL, lsl)
>
> -void trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
> +static void trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
>  {
>      static gen_helper_gvec_4 * const fns[4] = {
>          NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
> @@ -294,7 +329,7 @@ void trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, 
> uint32_t insn)
>      do_zpzz_ool(s, a, fns[a->esz]);
>  }
>
> -void trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
> +static void trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
>  {
>      static gen_helper_gvec_4 * const fns[4] = {
>          NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d

Should these changes to 'static' have been in a different patch, or was
that to avoid compiler warnings when the functions were introduced but not
used til this patch?

> diff --git a/target/arm/sve.decode b/target/arm/sve.decode
> index 68a1823b72..b40d7dc9a2 100644
> --- a/target/arm/sve.decode
> +++ b/target/arm/sve.decode
> @@ -68,6 +68,9 @@
>  # Three prediate operand, with governing predicate, flag setting
>  @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4    &rprr_s
>
> +# Three operand, vector element size
> address@hidden      ........ esz:2 . rm:5  ... ...  rn:5 rd:5       &rrr_esz
> +
>  # Two register operand, with governing predicate, vector element size
>  @rdn_pg_rm     ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
>                 &rprr_esz rn=%reg_movprfx
> @@ -205,6 +208,16 @@ MLS                00000100 .. 0 ..... 011 ... ..... 
> .....   @rda_pg_rn_rm
>  MLA            00000100 .. 0 ..... 110 ... ..... .....   @rdn_pg_ra_rm # MAD
>  MLS            00000100 .. 0 ..... 111 ... ..... .....   @rdn_pg_ra_rm # MSB
>
> +### SVE Integer Arithmetic - Unpredicated Group
> +
> +# SVE integer add/subtract vectors (unpredicated)
> +ADD_zzz                00000100 .. 1 ..... 000 000 ..... .....         
> @rd_rn_rm
> +SUB_zzz                00000100 .. 1 ..... 000 001 ..... .....         
> @rd_rn_rm
> +SQADD_zzz      00000100 .. 1 ..... 000 100 ..... .....         @rd_rn_rm
> +UQADD_zzz      00000100 .. 1 ..... 000 101 ..... .....         @rd_rn_rm
> +SQSUB_zzz      00000100 .. 1 ..... 000 110 ..... .....         @rd_rn_rm
> +UQSUB_zzz      00000100 .. 1 ..... 000 111 ..... .....         @rd_rn_rm

Misaligned lines for ADD and SUB.

Otherwise

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM