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[Qemu-devel] [PATCH v6 20/23] SiFive RISC-V Test Finisher
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v6 20/23] SiFive RISC-V Test Finisher |
Date: |
Fri, 23 Feb 2018 13:12:06 +1300 |
Test finisher memory mapped device used to exit simulation.
Signed-off-by: Michael Clark <address@hidden>
---
hw/riscv/sifive_test.c | 99 ++++++++++++++++++++++++++++++++++++++++++
include/hw/riscv/sifive_test.h | 48 ++++++++++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 hw/riscv/sifive_test.c
create mode 100644 include/hw/riscv/sifive_test.h
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
new file mode 100644
index 0000000..9696f15
--- /dev/null
+++ b/hw/riscv/sifive_test.c
@@ -0,0 +1,99 @@
+/*
+ * QEMU SiFive Test Finisher
+ *
+ * Copyright (c) 2018 SiFive, Inc.
+ *
+ * Test finisher memory mapped device used to exit simulation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "target/riscv/cpu.h"
+#include "hw/riscv/sifive_test.h"
+
+static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ return 0;
+}
+
+static void sifive_test_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ if (addr == 0) {
+ int status = val64 & 0xffff;
+ int code = (val64 >> 16) & 0xffff;
+ switch (status) {
+ case FINISHER_FAIL:
+ exit(code);
+ case FINISHER_PASS:
+ exit(0);
+ default:
+ break;
+ }
+ }
+ hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
+ __func__, (int)addr, val64);
+}
+
+static const MemoryRegionOps sifive_test_ops = {
+ .read = sifive_test_read,
+ .write = sifive_test_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void sifive_test_init(Object *obj)
+{
+ SiFiveTestState *s = SIFIVE_TEST(obj);
+
+ memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
+ TYPE_SIFIVE_TEST, 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static const TypeInfo sifive_test_info = {
+ .name = TYPE_SIFIVE_TEST,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SiFiveTestState),
+ .instance_init = sifive_test_init,
+};
+
+static void sifive_test_register_types(void)
+{
+ type_register_static(&sifive_test_info);
+}
+
+type_init(sifive_test_register_types)
+
+
+/*
+ * Create Test device.
+ */
+DeviceState *sifive_test_create(hwaddr addr)
+{
+ DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+ return dev;
+}
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
new file mode 100644
index 0000000..6a0f5bb
--- /dev/null
+++ b/include/hw/riscv/sifive_test.h
@@ -0,0 +1,48 @@
+/*
+ * QEMU Test Finisher interface
+ *
+ * Copyright (c) 2018 SiFive, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_SIFIVE_TEST_H
+#define HW_SIFIVE_TEST_H
+
+#define TYPE_SIFIVE_TEST "riscv.sifive.test"
+
+#define SIFIVE_TEST(obj) \
+ OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
+
+typedef struct SiFiveTestState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion mmio;
+} SiFiveTestState;
+
+enum {
+ FINISHER_FAIL = 0x3333,
+ FINISHER_PASS = 0x5555
+};
+
+DeviceState *sifive_test_create(hwaddr addr);
+
+#endif
--
2.7.0
- [Qemu-devel] [PATCH v6 10/23] RISC-V Linux User Emulation, (continued)
- [Qemu-devel] [PATCH v6 10/23] RISC-V Linux User Emulation, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 05/23] RISC-V CPU Helpers, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 13/23] RISC-V HART Array, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 17/23] RISC-V VirtIO Machine, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 23/23] RISC-V Build Infrastructure, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 04/23] RISC-V Disassembler, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 22/23] SiFive Freedom U500 RISC-V Machine, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 18/23] SiFive RISC-V UART Device, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 15/23] SiFive RISC-V PLIC Block, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 16/23] RISC-V Spike Machines, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 20/23] SiFive RISC-V Test Finisher,
Michael Clark <=
- [Qemu-devel] [PATCH v6 12/23] RISC-V HTIF Console, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 14/23] SiFive RISC-V CLINT Block, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 21/23] SiFive Freedom E300 RISC-V Machine, Michael Clark, 2018/02/22
- Re: [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission, no-reply, 2018/02/22
- Re: [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission, Daniel P . Berrangé, 2018/02/23