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[Qemu-devel] [PULL 19/21] target/arm: Add AIRCR to vmstate struct
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/21] target/arm: Add AIRCR to vmstate struct |
Date: |
Thu, 15 Feb 2018 13:57:00 +0000 |
In commit commit 3b2e934463121 we added support for the AIRCR
register holding state, but forgot to add it to the vmstate
structs. Since it only holds r/w state if the security extension
is implemented, we can just add it to vmstate_m_security.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/machine.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 30fb1454a6..25cdf4d581 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -423,6 +423,10 @@ static const VMStateDescription vmstate_m_security = {
VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),
VMSTATE_UINT32(env.sau.ctrl, ARMCPU),
VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),
+ /* AIRCR is not secure-only, but our implementation is R/O if the
+ * security extension is unimplemented, so we migrate it here.
+ */
+ VMSTATE_UINT32(env.v7m.aircr, ARMCPU),
VMSTATE_END_OF_LIST()
}
};
--
2.16.1
- [Qemu-devel] [PULL 15/21] hw/intc/armv7m_nvic: Implement cache ID registers, (continued)
- [Qemu-devel] [PULL 15/21] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 16/21] hw/intc/armv7m_nvic: Implement SCR, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 01/21] hw/arm/aspeed: directly map the serial device to the system address space, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 21/21] target/arm: Implement v8M MSPLIM and PSPLIM registers, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 17/21] target/arm: Implement writing to CONTROL_NS for v8M, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 04/21] raspi: Raspberry Pi 3 support, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 20/21] target/arm: Migrate v7m.other_sp, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 18/21] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 03/21] bcm2836: Make CPU type configurable, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 13/21] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops, Peter Maydell, 2018/02/15
- [Qemu-devel] [PULL 19/21] target/arm: Add AIRCR to vmstate struct,
Peter Maydell <=