Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Emilio G. Cota]

On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
> 
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
> 
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
(snip)
> +++ b/target/riscv/translate.c
(snip)
> +enum {
> +    BS_NONE     = 0, /* When seen outside of translation while loop, 
> indicates
> +                     need to exit tb due to end of page. */
> +    BS_STOP     = 1, /* Need to exit tb for syscall, sret, etc. */

Are we planning to use BS_STOP in the future? I see it has no setters,
although we check for it in gen_intermediate_code:

(snip)
> +    switch (ctx.bstate) {
> +    case BS_STOP:
> +        gen_goto_tb(&ctx, 0, ctx.pc);
> +        break;
> +    case BS_NONE: /* handle end of page - DO NOT CHAIN. See gen_goto_tb. */

Should we get rid of it?

                Emilio