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[Qemu-devel] [PULL 24/30] target/arm: Add predicate registers for SVE
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/30] target/arm: Add predicate registers for SVE |
Date: |
Fri, 9 Feb 2018 11:03:08 +0000 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0e3cd52aa3..966d2fdbb1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -188,6 +188,13 @@ typedef struct ARMVectorReg {
uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
} ARMVectorReg;
+/* In AArch32 mode, predicate registers do not exist at all. */
+#ifdef TARGET_AARCH64
+typedef struct ARMPredicateReg {
+ uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
+} ARMPredicateReg;
+#endif
+
typedef struct CPUARMState {
/* Regs for current mode. */
@@ -515,6 +522,11 @@ typedef struct CPUARMState {
struct {
ARMVectorReg zregs[32];
+#ifdef TARGET_AARCH64
+ /* Store FFR as pregs[16] to make it easier to treat as any other. */
+ ARMPredicateReg pregs[17];
+#endif
+
uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */
int vec_len;
--
2.16.1
- [Qemu-devel] [PULL 17/30] i.MX: Add code to emulate i.MX7 SNVS IP-block, (continued)
- [Qemu-devel] [PULL 17/30] i.MX: Add code to emulate i.MX7 SNVS IP-block, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 15/30] i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 20/30] i.MX: Add implementation of i.MX7 GPR IP block, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 29/30] target/arm/translate.c: Fix missing 'break' for TT insns, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 26/30] target/arm: Add ZCR_ELx, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 18/30] i.MX: Add code to emulate GPCv2 IP block, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 25/30] target/arm: Add SVE to migration state, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 03/30] target/arm: Add ignore_stackfaults argument to v7m_exception_taken(), Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 19/30] i.MX: Add i.MX7 GPT variant, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 06/30] target/arm: Make exception vector loads honour the SAU, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 24/30] target/arm: Add predicate registers for SVE,
Peter Maydell <=
- [Qemu-devel] [PULL 22/30] hw/arm: Move virt's PSCI DT fixup code to arm/boot.c, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 04/30] target/arm: Make v7M exception entry stack push check MPU, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 30/30] hw/core/generic-loader: Allow PC to be set on command line, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 09/30] target/arm: implement SHA-3 instructions, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 23/30] target/arm: Expand vector registers for SVE, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 16/30] i.MX: Add code to emulate i.MX2 watchdog IP block, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 27/30] target/arm: Add SVE state to TB->FLAGS, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 28/30] target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM, Peter Maydell, 2018/02/09
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2018/02/09