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[Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register |
Date: |
Thu, 8 Feb 2018 13:48:06 -0300 |
As per the Spec v3.00
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
include/hw/sd/sdhci.h | 2 +-
hw/sd/sdhci.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 40798aed58..e1974306f9 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -58,7 +58,7 @@ typedef struct SDHCIState {
uint16_t cmdreg; /* Command Register */
uint32_t rspreg[4]; /* Response Registers 0-3 */
uint32_t prnsts; /* Present State Register */
- uint8_t hostctl; /* Host Control Register */
+ uint8_t hostctl1; /* Host Control Register */
uint8_t pwrcon; /* Power control Register */
uint8_t blkgap; /* Block Gap Control Register */
uint8_t wakcon; /* WakeUp Control Register */
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 68ba225462..bcdf8529cc 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -691,7 +691,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr
*dscr)
uint32_t adma1 = 0;
uint64_t adma2 = 0;
hwaddr entry_addr = (hwaddr)s->admasysaddr;
- switch (SDHC_DMA_TYPE(s->hostctl)) {
+ switch (SDHC_DMA_TYPE(s->hostctl1)) {
case SDHC_CTRL_ADMA2_32:
dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2,
sizeof(adma2));
@@ -880,7 +880,7 @@ static void sdhci_data_transfer(void *opaque)
SDHCIState *s = (SDHCIState *)opaque;
if (s->trnmod & SDHC_TRNS_DMA) {
- switch (SDHC_DMA_TYPE(s->hostctl)) {
+ switch (SDHC_DMA_TYPE(s->hostctl1)) {
case SDHC_CTRL_SDMA:
if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
sdhci_sdma_transfer_single_block(s);
@@ -989,7 +989,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = s->prnsts;
break;
case SDHC_HOSTCTL:
- ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
+ ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) |
(s->wakcon << 24);
break;
case SDHC_CLKCON:
@@ -1107,7 +1107,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
MASKED_WRITE(s->sdmasysad, mask, value);
/* Writing to last byte of sdmasysad might trigger transfer */
if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt
&&
- s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
+ s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
if (s->trnmod & SDHC_TRNS_MULTI) {
sdhci_sdma_transfer_multi_blocks(s);
} else {
@@ -1159,7 +1159,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
if (!(mask & 0xFF0000)) {
sdhci_blkgap_write(s, value >> 16);
}
- MASKED_WRITE(s->hostctl, mask, value);
+ MASKED_WRITE(s->hostctl1, mask, value);
MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
@@ -1378,7 +1378,7 @@ const VMStateDescription sdhci_vmstate = {
VMSTATE_UINT16(cmdreg, SDHCIState),
VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
VMSTATE_UINT32(prnsts, SDHCIState),
- VMSTATE_UINT8(hostctl, SDHCIState),
+ VMSTATE_UINT8(hostctl1, SDHCIState),
VMSTATE_UINT8(pwrcon, SDHCIState),
VMSTATE_UINT8(blkgap, SDHCIState),
VMSTATE_UINT8(wakcon, SDHCIState),
--
2.16.1
- [Qemu-devel] [PATCH v11 06/30] sdhci: add qtest to check the SD Spec version, (continued)
- [Qemu-devel] [PATCH v11 06/30] sdhci: add qtest to check the SD Spec version, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 07/30] sdhci: add a 'spec_version property' (default to v2), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 09/30] sdhci: simplify sdhci_get_fifolen(), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 08/30] sdhci: use a numeric value for the default CAPAB register, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 10/30] sdhci: check the Spec v1 capabilities correctness, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 12/30] sdhci: Fix 64-bit ADMA2, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 13/30] sdhci: check Spec v2 capabilities (DMA and 64-bit bus), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 14/30] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64(), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 15/30] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 20/30] sdbus: add trace events, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 21/30] sdhci: implement UHS-I voltage switch, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 22/30] sdhci: implement CMD/DAT[] fields in the Present State register, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 27/30] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 28/30] sdhci: check Spec v3 capabilities qtest, Philippe Mathieu-Daudé, 2018/02/08