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Re: [Qemu-devel] [PATCH 6/7] hw/mips_cpc: kick a VP when putting it into
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH 6/7] hw/mips_cpc: kick a VP when putting it into Run state |
Date: |
Fri, 19 Jan 2018 16:47:14 +0000 |
User-agent: |
mu4e 1.0-alpha3; emacs 26.0.91 |
Aleksandar Markovic <address@hidden> writes:
> From: Miodrag Dinic <address@hidden>
>
> While testing mttcg VP0 could get gets stuck in a loop waiting
> for other VPs to come up (which never actually happens). To fix this,
> kick VPs while they are being powered up by Cluster Power Controller
> in a async task which is triggered once the host thread is being
> spawned.
>
> Signed-off-by: Miodrag Dinic <address@hidden>
> Signed-off-by: Leon Alrae <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
> hw/misc/mips_cpc.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
> index 6d34574..105a109 100644
> --- a/hw/misc/mips_cpc.c
> +++ b/hw/misc/mips_cpc.c
> @@ -30,6 +30,14 @@ static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
> return (1ULL << cpc->num_vp) - 1;
> }
>
> +static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
> +{
> + MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
Is MIPSCPCState part of the CPUState or a shared structure? If it is a
shared structure you may need to use safe work or have some form of
locking to prevent races.
> +
> + cpu_reset(cs);
> + cpc->vp_running |= 1ULL << cs->cpu_index;
> +}
> +
> static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
> {
> CPUState *cs = first_cpu;
> @@ -37,8 +45,13 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
> CPU_FOREACH(cs) {
> uint64_t i = 1ULL << cs->cpu_index;
> if (i & vp_run & ~cpc->vp_running) {
> - cpu_reset(cs);
> - cpc->vp_running |= i;
> + /*
> + * To avoid racing with a CPU we are just kicking off.
> + * We do the final bit of preparation for the work in
> + * the target CPUs context.
> + */
> + async_run_on_cpu(cs, mips_cpu_reset_async_work,
> + RUN_ON_CPU_HOST_PTR(cpc));
> }
> }
> }
--
Alex Bennée
- [Qemu-devel] [PATCH 0/7] target-mips: support MTTCG feature, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 4/7] hw/mips_int: hold BQL for all interrupt requests, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 6/7] hw/mips_cpc: kick a VP when putting it into Run state, Aleksandar Markovic, 2018/01/19
- Re: [Qemu-devel] [PATCH 6/7] hw/mips_cpc: kick a VP when putting it into Run state,
Alex Bennée <=
- [Qemu-devel] [PATCH 5/7] target/mips: hold BQL in mips_vpe_wake(), Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 1/7] target/mips: compare virtual addresses in LL/SC sequence, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 2/7] target/mips: reimplement SC instruction and use cmpxchg, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 7/7] target/mips: introduce MTTCG-enabled builds, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 3/7] Revert "target/mips: hold BQL for timer interrupts", Aleksandar Markovic, 2018/01/19