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[Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M |
Date: |
Tue, 16 Jan 2018 13:33:57 +0000 |
For PMSAv7, the v7A/R Arm ARM defines that setting AP to 0b111
is an UNPREDICTABLE reserved combination. However, for v7M
this value is documented as having the same behaviour as 0b110:
read-only for both privileged and unprivileged. Accept this
value on an M profile core rather than treating it as a guest
error and a no-access page.
Reported-by: Andy Gross <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d1395f9..eb80f79 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9272,6 +9272,13 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
uint32_t address,
case 6:
*prot |= PAGE_READ | PAGE_EXEC;
break;
+ case 7:
+ /* for v7M, same as 6; for R profile a reserved value */
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ *prot |= PAGE_READ | PAGE_EXEC;
+ break;
+ }
+ /* fall through */
default:
qemu_log_mask(LOG_GUEST_ERROR,
"DRACR[%d]: Bad value for AP bits: 0x%"
@@ -9290,6 +9297,13 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
uint32_t address,
case 6:
*prot |= PAGE_READ | PAGE_EXEC;
break;
+ case 7:
+ /* for v7M, same as 6; for R profile a reserved value */
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ *prot |= PAGE_READ | PAGE_EXEC;
+ break;
+ }
+ /* fall through */
default:
qemu_log_mask(LOG_GUEST_ERROR,
"DRACR[%d]: Bad value for AP bits: 0x%"
--
2.7.4
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 10/24] target/arm: Add fp16 support to vfp_expand_imm, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 12/24] sdhci: remove dead code, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 03/24] hw/arm/virt: Add virt-2.12 machine type, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 07/24] hw/sd/ssi-sd: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 04/24] target/arm: Handle page table walk load failures correctly, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 19/24] sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h", Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 09/24] target/arm: Split out vfp_expand_imm, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 15/24] sdhci: refactor common sysbus/pci realize() into sdhci_common_realize(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 06/24] hw/sd/milkymist-memcard: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M,
Peter Maydell <=
- [Qemu-devel] [PULL 08/24] hw/sd/omap_mmc: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 05/24] hw/sd/pl181: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 13/24] sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 14/24] sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 20/24] sdhci: rename the SDHC_CAPAB register, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 23/24] sdhci: fix the PCI device, using the PCI address space for DMA, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 22/24] sdhci: Implement write method of ACMD12ERRSTS register, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 11/24] sdhci: clean up includes, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword accesses to CFSR, Peter Maydell, 2018/01/16