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Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure |
Date: |
Fri, 12 Jan 2018 07:43:20 +1300 |
On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake <address@hidden> wrote:
> On 01/10/2018 08:22 PM, Michael Clark wrote:
> > This adds RISC-V into the build system enabling the following targets:
> >
> > - riscv32-softmmu
> > - riscv64-softmmu
> > - riscv32-linux-user
> > - riscv64-linux-user
> >
> > This adds defaults configs for RISC-V, enables the build for the RISC-V
> > CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
> > script is updated to add the RISC-V ELF magic.
> >
> > +++ b/qapi-schema.json
> > @@ -413,7 +413,7 @@
> > # Since: 2.6
> > ##
> > { 'enum': 'CpuInfoArch',
> > - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
> > + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ]
> }
>
> Still missing documentation that riscv was added in 2.12 (see my
> comments on v1).
My apologies. I had a look at QKeyCode and it was not clear to me how to
specify since on an enum value vs a field.
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -411,6 +411,9 @@
# @query-cpus.
why is this @query-cpus and not @CpuInfoArch: as is the case for @QKeyCode?
#
# Since: 2.6
+#
+# @riscv: since 2.12
+#
##
{ 'enum': 'CpuInfoArch',
'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] }
Is this correct?
> --- /dev/null
> > +++ b/target/riscv/trace-events
> > @@ -0,0 +1 @@
> > +# See docs/devel/tracing.txt for syntax documentation.
> >
>
> Do we really need this file if you don't have any traces yet?
>
I'll remove the file or add some tracing in the next spin.
- [Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection, (continued)
- [Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 12/21] RISC-V HART Array, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 RISC-V Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/10