Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

[Michael Clark]

On Fri, Jan 12, 2018 at 3:37 AM, Richard Henderson <
address@hidden> wrote:

> On 01/10/2018 06:21 PM, Michael Clark wrote:
> > +static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
> target_ulong *pc,
> > +                                        target_ulong *cs_base, uint32_t
> *flags)
> > +{
> > +    *pc = env->pc;
> > +    *cs_base = 0;
> > +    *flags = 0; /* necessary to avoid compiler warning */
> > +}
>
> Actually, at minimum you have to put enough into flags to differentiate
> machine
> vs supervisor vs user mode.  Otherwise you can wind up running a previously
> translated block with the wrong permissions.
>
> The patch I saw from Stefan O'Rear would do nicely.
>

OK. I didn't see the patch. I'll trawl through my email for the last couple
of weeks before the next spin.

So any CPU state that can effect translation should be in flags?

Assuming that is the case, we could probably join mode with the lower 26
bits of misa and we probably should do a tb_flush on misa CSR writes if any
bits are changed. i.e. if extensions such as MAFDC are added or
removed (muldiv, atomics, fp-single, fp-double, compressed).