[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition |
Date: |
Thu, 11 Jan 2018 06:37:50 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 |
On 01/10/2018 06:21 PM, Michael Clark wrote:
> +static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> + target_ulong *cs_base, uint32_t
> *flags)
> +{
> + *pc = env->pc;
> + *cs_base = 0;
> + *flags = 0; /* necessary to avoid compiler warning */
> +}
Actually, at minimum you have to put enough into flags to differentiate machine
vs supervisor vs user mode. Otherwise you can wind up running a previously
translated block with the wrong permissions.
The patch I saw from Stefan O'Rear would do nicely.
r~
[Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 12/21] RISC-V HART Array, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/10
[Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/10