[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v5 01/17] target-m68k: sync CC_OP before gen_jmp_tb(
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v5 01/17] target-m68k: sync CC_OP before gen_jmp_tb() |
Date: |
Tue, 2 Jan 2018 02:10:16 +0100 |
And remove update_cc_op() from gen_exception() because there is
one in gen_jmp_im().
Signed-off-by: Laurent Vivier <address@hidden>
---
target/m68k/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index bbda7399ec..0e9d651a2a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -270,7 +270,6 @@ static void gen_raise_exception(int nr)
static void gen_exception(DisasContext *s, uint32_t where, int nr)
{
- update_cc_op(s);
gen_jmp_im(s, where);
gen_raise_exception(nr);
}
@@ -2897,6 +2896,7 @@ DISAS_INSN(branch)
gen_jmp_tb(s, 0, s->pc);
} else {
/* Unconditional branch. */
+ update_cc_op(s);
gen_jmp_tb(s, 0, base + offset);
}
}
@@ -4875,6 +4875,7 @@ static void gen_fjmpcc(DisasContext *s, int cond,
TCGLabel *l1)
DisasCompare c;
gen_fcc_cond(&c, s, cond);
+ update_cc_op(s);
tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
free_cond(&c);
}
--
2.14.3
- [Qemu-devel] [PATCH v5 00/17] target/m68k: supervisor mode (part 1), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 02/17] target/m68k: fix gen_get_ccr(), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 01/17] target-m68k: sync CC_OP before gen_jmp_tb(),
Laurent Vivier <=
- [Qemu-devel] [PATCH v5 06/17] target/m68k: manage 680x0 stack frames, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 04/17] target-m68k: use insn_pc to generate instruction fault address, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 14/17] target/m68k: add 680x0 "move to SR" instruction, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 12/17] target/m68k: implement fsave/frestore, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 17/17] target/m68k: fix m68k_cpu_dump_state(), Laurent Vivier, 2018/01/01