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[Qemu-devel] [PATCH v3 28/42] hw/arm/xilinx_zynq: implement SDHCI Spec v
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v3 28/42] hw/arm/xilinx_zynq: implement SDHCI Spec v2 |
Date: |
Fri, 29 Dec 2017 14:49:19 -0300 |
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/arm/xilinx_zynq.c | 64 ++++++++++++++++++++++++++++++++--------------------
1 file changed, 40 insertions(+), 24 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 1836a4ed45..9a106db7b7 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -165,10 +165,8 @@ static void zynq_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
- DeviceState *dev, *carddev;
+ DeviceState *dev;
SysBusDevice *busdev;
- DriveInfo *di;
- BlockBackend *blk;
qemu_irq pic[64];
int n;
@@ -247,27 +245,45 @@ static void zynq_init(MachineState *machine)
gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
-
- di = drive_get_next(IF_SD);
- blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
- qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
-
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
-
- di = drive_get_next(IF_SD);
- blk = di ? blk_by_legacy_dinfo(di) : NULL;
- carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
- qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
- object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
+ for (n = 0; n < 2; n++) {
+ int hci_irq = n ? 79 : 56;
+ hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
+ DriveInfo *di;
+ BlockBackend *blk;
+ DeviceState *carddev;
+
+ /* Compatible with:
+ * - SD Host Controller Specification Version 2.0 Part A2
+ * - SDIO Specification Version 2.0
+ * - MMC Specification Version 3.31
+ *
+ * - SDMA (single operation DMA)
+ * - ADMA1 (4 KB boundary limited DMA)
+ * - ADMA2
+ *
+ * - up to seven functions in SD1, SD4, but does not support SPI mode
+ * - SD high-speed (SDHS) card
+ * - SD High Capacity (SDHC) card
+ *
+ * - Low-speed, 1 KHz to 400 KHz
+ * - Full-speed, 1 MHz to 50 MHz (25 MB/sec)
+ */
+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
+ qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+ qdev_prop_set_bit(dev, "adma1", true);
+ qdev_prop_set_bit(dev, "high-speed", true);
+ qdev_prop_set_uint16(dev, "max-block-length", 1024);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
+
+ di = drive_get_next(IF_SD);
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
+ carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized",
+ &error_fatal);
+ }
dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
qdev_init_nofail(dev);
--
2.15.1
- [Qemu-devel] [PATCH v3 16/42] sdhci: use deposit64() on admasysaddr, (continued)
- [Qemu-devel] [PATCH v3 16/42] sdhci: use deposit64() on admasysaddr, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 17/42] sdhci: add a "dma-memory" property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 18/42] sdhci: add a spec_version property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 19/42] sdhci: add basic Spec v1 capabilities, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 20/42] sdhci: add max-block-length capability (Spec v1), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 22/42] sdhci: add DMA and 64-bit capabilities (Spec v2), Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 23/42] sdhci: default to Spec v2, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 24/42] sdhci: add a 'dma' shortcut property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 26/42] sdhci: Fix 64-bit ADMA2, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 27/42] hw/arm/exynos4210: implement SDHCI Spec v2, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 28/42] hw/arm/xilinx_zynq: implement SDHCI Spec v2,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v3 29/42] sdhci: add qtest to check the SD Spec version, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 30/42] sdhci: check Spec v2 capabilities qtest, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 32/42] sdhci: rename the hostctl1 register, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 33/42] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 34/42] hw/arm/fsl-imx6: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 35/42] hw/arm/xilinx_zynqmp: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 36/42] sdhci: check Spec v3 capabilities qtest, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 37/42] sdhci: remove the deprecated 'capareg' property, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 39/42] sdhci: add a check_capab_baseclock() qtest, Philippe Mathieu-Daudé, 2017/12/29
- [Qemu-devel] [PATCH v3 38/42] sdhci: add check_capab_readonly() qtest, Philippe Mathieu-Daudé, 2017/12/29