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[Qemu-devel] [RFC 00/23] target/arm: decode generator and initial sve pa
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [RFC 00/23] target/arm: decode generator and initial sve patches |
Date: |
Mon, 18 Dec 2017 09:45:29 -0800 |
The most important part here, for review, is the first patch.
I add a code generator, writen in python, which takes an input file
that describes the opcode bits and field bits of the instructions,
and outputs a function that does all of the decoding.
The subsequent patches begin to add SVE support and also demonstrate
how I envision how both the decoder and the tcg host vector support
are to be used. Thus, review of the direction would be appreciated
before there are another 100 patches along the same style.
r~
Richard Henderson (23):
scripts: Add decodetree.py
target/arm: Add SVE decode skeleton
target/arm: Implement SVE Bitwise Logical - Unpredicated Group
target/arm: Implement PTRUE, PFALSE, SETFFR
target/arm: Implement SVE predicate logical operations
target/arm: Implement SVE load vector/predicate
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
target/arm: Handle SVE registers in write_fp_dreg
target/arm: Handle SVE registers when using clear_vec_high
target/arm: Implement SVE Integer Reduction Group
target/arm: Implement SVE bitwise shift by immediate (predicated)
target/arm: Implement SVE bitwise shift by vector (predicated)
target/arm: Implement SVE bitwise shift by wide elements (predicated)
target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group
target/arm: Implement SVE Integer Multiply-Add Group
target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
target/arm: Implement SVE Index Generation Group
target/arm: Implement SVE Stack Allocation Group
target/arm: Implement SVE Bitwise Shift - Unpredicated Group
target/arm: Implement SVE Compute Vector Address Group
target/arm: Implement SVE floating-point exponential accelerator
target/arm: Implement SVE floating-point trig select coefficient
target/arm: Implement SVE Element Count Group, register destinations
target/arm/helper-sve.h | 409 ++++++++++++++
target/arm/helper.h | 1 +
target/arm/translate-a64.h | 112 ++++
target/arm/sve_helper.c | 1177 +++++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 272 +++------
target/arm/translate-sve.c | 1313 ++++++++++++++++++++++++++++++++++++++++++++
.gitignore | 1 +
scripts/decodetree.py | 984 +++++++++++++++++++++++++++++++++
target/arm/Makefile.objs | 11 +
target/arm/sve.def | 328 +++++++++++
10 files changed, 4418 insertions(+), 190 deletions(-)
create mode 100644 target/arm/helper-sve.h
create mode 100644 target/arm/translate-a64.h
create mode 100644 target/arm/sve_helper.c
create mode 100644 target/arm/translate-sve.c
create mode 100755 scripts/decodetree.py
create mode 100644 target/arm/sve.def
--
2.14.3
- [Qemu-devel] [RFC 00/23] target/arm: decode generator and initial sve patches,
Richard Henderson <=
- [Qemu-devel] [PATCH 02/23] target/arm: Add SVE decode skeleton, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 01/23] scripts: Add decodetree.py, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 04/23] target/arm: Implement PTRUE, PFALSE, SETFFR, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 03/23] target/arm: Implement SVE Bitwise Logical - Unpredicated Group, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 05/23] target/arm: Implement SVE predicate logical operations, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 06/23] target/arm: Implement SVE load vector/predicate, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 08/23] target/arm: Handle SVE registers in write_fp_dreg, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 07/23] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 09/23] target/arm: Handle SVE registers when using clear_vec_high, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH 10/23] target/arm: Implement SVE Integer Reduction Group, Richard Henderson, 2017/12/18