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[Qemu-devel] [PATCH v7 15/26] target/arm: Use vector infrastructure for
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v7 15/26] target/arm: Use vector infrastructure for aa64 compares |
Date: |
Mon, 18 Dec 2017 09:17:47 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 96 ++++++++++++++++++++++++++++++----------------
1 file changed, 62 insertions(+), 34 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c47faa5633..1ea7e37b03 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7115,6 +7115,28 @@ static void
disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
}
}
+/* CMTST : test is "if (X & Y != 0)". */
+static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_and_i32(d, a, b);
+ tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0);
+ tcg_gen_neg_i32(d, d);
+}
+
+static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_and_i64(d, a, b);
+ tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0);
+ tcg_gen_neg_i64(d, d);
+}
+
+static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_and_vec(vece, d, a, b);
+ tcg_gen_dupi_vec(vece, a, 0);
+ tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
+}
+
static void handle_3same_64(DisasContext *s, int opcode, bool u,
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
{
@@ -7158,10 +7180,7 @@ static void handle_3same_64(DisasContext *s, int opcode,
bool u,
cond = TCG_COND_EQ;
goto do_cmop;
}
- /* CMTST : test is "if (X & Y != 0)". */
- tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
- tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
- tcg_gen_neg_i64(tcg_rd, tcg_rd);
+ gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm);
break;
case 0x8: /* SSHL, USHL */
if (u) {
@@ -9684,6 +9703,7 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
int rd = extract32(insn, 0, 5);
int pass;
GVecGen3Fn *gvec_op;
+ TCGCond cond;
switch (opcode) {
case 0x13: /* MUL, PMUL */
@@ -9731,6 +9751,44 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s));
return;
+ case 0x11:
+ if (u) { /* CMEQ */
+ cond = TCG_COND_EQ;
+ goto do_gvec_cmp;
+ } else { /* CMTST */
+ static const GVecGen3 cmtst_op[4] = {
+ { .fni4 = gen_helper_neon_tst_u8,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_8 },
+ { .fni4 = gen_helper_neon_tst_u16,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_cmtst_i32,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_cmtst_i64,
+ .fniv = gen_cmtst_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ &cmtst_op[size]);
+ }
+ return;
+ case 0x06: /* CMGT, CMHI */
+ cond = u ? TCG_COND_GTU : TCG_COND_GT;
+ goto do_gvec_cmp;
+ case 0x07: /* CMGE, CMHS */
+ cond = u ? TCG_COND_GEU : TCG_COND_GE;
+ do_gvec_cmp:
+ tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
}
if (size == 3) {
@@ -9813,26 +9871,6 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genenvfn = fns[size][u];
break;
}
- case 0x6: /* CMGT, CMHI */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 },
- { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 },
- { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 },
- };
- genfn = fns[size][u];
- break;
- }
- case 0x7: /* CMGE, CMHS */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 },
- { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 },
- { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x8: /* SSHL, USHL */
{
static NeonGenTwoOpFn * const fns[3][2] = {
@@ -9905,16 +9943,6 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genfn = fns[size][u];
break;
}
- case 0x11: /* CMTST, CMEQ */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 },
- { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 },
- { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x13: /* MUL, PMUL */
if (u) {
/* PMUL */
--
2.14.3
- [Qemu-devel] [PATCH v7 08/26] tcg/i386: Add vector operations, (continued)
- [Qemu-devel] [PATCH v7 08/26] tcg/i386: Add vector operations, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 14/26] tcg: Add generic vector ops for comparisons, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 13/26] target/arm: Use vector infrastructure for aa64 constant shifts, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 17/26] tcg: Add generic vector ops for multiplication, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 12/26] tcg: Add generic vector ops for constant shifts, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 20/26] target/arm: Use vector infrastructure for aa64 widening shifts, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 16/26] tcg/i386: Add vector operations/expansions for shift/cmp/interleave, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 02/26] tcg: Add generic vector expanders, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 10/26] tcg: Add generic vector ops for interleave, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 18/26] target/arm: Use vector infrastructure for aa64 multiplies, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 15/26] target/arm: Use vector infrastructure for aa64 compares,
Richard Henderson <=
- [Qemu-devel] [PATCH v7 19/26] tcg: Add generic vector ops for extension, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 21/26] tcg/i386: Add vector operations/expansions for mul/extend, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 23/26] tcg/optimize: Handle vector opcodes during optimize, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 24/26] tcg: Add support for 4 operand vector ops, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 25/26] tcg: Add support for 5 operand vector ops, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 22/26] tcg/aarch64: Add vector operations, Richard Henderson, 2017/12/18
- [Qemu-devel] [PATCH v7 26/26] tcg: Add generic helpers for saturating arithmetic, Richard Henderson, 2017/12/18