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[Qemu-devel] [PULL 10/24] spapr/rtas: disable the decrementer interrupt
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 10/24] spapr/rtas: disable the decrementer interrupt when a CPU is unplugged |
Date: |
Fri, 15 Dec 2017 16:54:21 +1100 |
From: Cédric Le Goater <address@hidden>
When a CPU is stopped with the 'stop-self' RTAS call, its state
'halted' is switched to 1 and, in this case, the MSR is not taken into
account anymore in the cpu_has_work() routine. Only the pending
hardware interrupts are checked with their LPCR:PECE* enablement bit.
If the DECR timer fires after 'stop-self' is called and before the CPU
'stop' state is reached, the nearly-dead CPU will have some work to do
and the guest will crash. This case happens very frequently with the
not yet upstream P9 XIVE exploitation mode. In XICS mode, the DECR is
occasionally fired but after 'stop' state, so no work is to be done
and the guest survives.
I suspect there is a race between the QEMU mainloop triggering the
timers and the TCG CPU thread but I could not quite identify the root
cause. To be safe, let's disable in the LPCR all the exceptions which
can cause an exit while the CPU is in power-saving mode and reenable
them when the CPU is started.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr_rtas.c | 11 +++++++++++
target/ppc/translate_init.c | 9 ++++++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index cdf0b607a0..858adb1bf3 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -162,6 +162,7 @@ static void rtas_start_cpu(PowerPCCPU *cpu_,
sPAPRMachineState *spapr,
if (cpu != NULL) {
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
if (!cs->halted) {
rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
@@ -174,6 +175,10 @@ static void rtas_start_cpu(PowerPCCPU *cpu_,
sPAPRMachineState *spapr,
kvm_cpu_synchronize_state(cs);
env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
+
+ /* Enable Power-saving mode Exit Cause exceptions for the new CPU */
+ env->spr[SPR_LPCR] |= pcc->lpcr_pm;
+
env->nip = start;
env->gpr[3] = r3;
cs->halted = 0;
@@ -197,6 +202,7 @@ static void rtas_stop_self(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
cs->halted = 1;
qemu_cpu_kick(cs);
@@ -210,6 +216,11 @@ static void rtas_stop_self(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
* no need to bother with specific bits, we just clear it.
*/
env->msr = 0;
+
+ /* Disable Power-saving mode Exit Cause exceptions for the CPU.
+ * This could deliver an interrupt on a dying CPU and crash the
+ * guest */
+ env->spr[SPR_LPCR] &= ~pcc->lpcr_pm;
}
static inline int sysparm_st(target_ulong addr, target_ulong len,
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 074c3a1d45..70ff15a51a 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8911,6 +8911,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
PPCVirtualHypervisor *vhyp)
CPUPPCState *env = &cpu->env;
ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
+ CPUState *cs = CPU(cpu);
cpu->vhyp = vhyp;
@@ -8953,10 +8954,12 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
PPCVirtualHypervisor *vhyp)
}
}
- /* Also set the power-saving mode bits which depend on the CPU
- * family
+ /* Only enable Power-saving mode Exit Cause exceptions on the boot
+ * CPU. The RTAS command start-cpu will enable them on secondaries.
*/
- lpcr->default_value |= pcc->lpcr_pm;
+ if (cs == first_cpu) {
+ lpcr->default_value |= pcc->lpcr_pm;
+ }
/* We should be followed by a CPU reset but update the active value
* just in case...
--
2.14.3
- [Qemu-devel] [PULL 00/24] ppc-for-2.12 queue 20171215, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 01/24] target/ppc: Use tcg_gen_lookup_and_goto_ptr, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 02/24] ppc/xics: remove useless if condition, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 03/24] spapr: Add pseries-2.12 machine type, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 04/24] spapr_cpu_core: instantiate CPUs separately, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 06/24] nvram: add AT24Cx i2c eeprom, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 05/24] e500: name openpic and pci host bridge, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 10/24] spapr/rtas: disable the decrementer interrupt when a CPU is unplugged,
David Gibson <=
- [Qemu-devel] [PULL 12/24] spapr/rtas: do not reset the MSR in stop-self command, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 09/24] e500: fix pci host bridge class/type, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 16/24] spapr: introduce a spapr_irq_set_lsi() helper, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 13/24] ppc/xics: introduce an icp_create() helper, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 20/24] spapr_events: drop bogus cell from "interrupt-ranges" property, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 07/24] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 14/24] ppc/xics: assign of the CPU 'intc' pointer under the core, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 15/24] spapr: move the IRQ allocation routines under the machine, David Gibson, 2017/12/15
- [Qemu-devel] [PULL 08/24] openpic: debug w/ info_report(), David Gibson, 2017/12/15
- [Qemu-devel] [PULL 18/24] spapr: replace numa_get_node() with lookup in pc-dimm list, David Gibson, 2017/12/15