[Qemu-devel] [PATCH] test/i386 - Allow TCG to boot with > 1TB memory

[Antonio Huete Jiménez]

From daea6caf8d9e023d06a825a774b678d26d978209 Mon Sep 17 00:00:00 2001
From: Antonio Huete Jimenez <address@hidden>
Date: Tue, 12 Dec 2017 19:17:49 +0100
Subject: [PATCH] test/i386 - Allow TCG to boot with > 1TB memory.

Currently for TCG the cpu 'phys_bits' property can't be specified
as it is hardcoded to be either 36 or 40 bits.

This patch lets the user specify the physical address bits for the
cpu as long as it's between a defined range. It will fallback to
'default' values which are the current ones so the behaviour
when the property isn't specified remains as it is now.

Signed-off-by: Antonio Huete Jimenez <address@hidden>
---
 target/i386/cpu.c         | 11 +++++++----
 target/i386/cpu.h         | 15 +++++++++------
 target/i386/excp_helper.c |  2 +-
 3 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 045d66191f..63da043027 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3687,9 +3687,12 @@ static void x86_cpu_realizefn(DeviceState *dev,  
Error **errp)
                 return;
             }
         } else {
-            if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
-                error_setg(errp, "TCG only supports phys-bits=%u",
-                                  TCG_PHYS_ADDR_BITS);
+            if (cpu->phys_bits &&
+                (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
+                 cpu->phys_bits < 32)) {
+                error_setg(errp, "phys-bits should be between 32 and %u "
+                           " (but is %u)",
+                           TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
                 return;
             }
         }
@@ -3698,7 +3701,7 @@ static void x86_cpu_realizefn(DeviceState *dev,  
Error **errp)
          * is the value used by TCG (40).
          */
         if (cpu->phys_bits == 0) {
-            cpu->phys_bits = TCG_PHYS_ADDR_BITS;
+            cpu->phys_bits = DEFAULT_PHYS_ADDR_BITS;
         }
     } else {
         /* For 32 bit systems don't use the user set value, but keep
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b086b1528b..fcb7cc8b96 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -280,7 +280,6 @@
 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 #define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
 #define PG_ADDRESS_MASK  0x000ffffffffff000LL
-#define PG_HI_RSVD_MASK  (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
 #define PG_HI_USER_MASK  0x7ff0000000000000LL
 #define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
 #define PG_NX_MASK       (1ULL << PG_NX_BIT)
@@ -1498,15 +1497,19 @@ uint64_t cpu_get_tsc(CPUX86State *env);
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif

-/* XXX: This value should match the one returned by CPUID
- * and in exec.c */
+/*
+ * This value matches the one returned by CPUID when running in KVM mode
+ * but for TCG as the host might be a different architecture so rely on
+ * either what the user passed in the cpu property phys-bits or use the
+ * default value.
+ */
 # if defined(TARGET_X86_64)
-# define TCG_PHYS_ADDR_BITS 40
+# define DEFAULT_PHYS_ADDR_BITS 40
 # else
-# define TCG_PHYS_ADDR_BITS 36
+# define DEFAULT_PHYS_ADDR_BITS 36
 # endif

-#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
+#define PHYS_ADDR_MASK(cpu) MAKE_64BIT_MASK(0, cpu->phys_bits)

 #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model)

diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c
index cef44495ab..835c4379a9 100644
--- a/target/i386/excp_helper.c
+++ b/target/i386/excp_helper.c
@@ -173,7 +173,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
     int error_code = 0;
     int is_dirty, prot, page_size, is_write, is_user;
     hwaddr paddr;
-    uint64_t rsvd_mask = PG_HI_RSVD_MASK;
+    uint64_t rsvd_mask = (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK(cpu));
     uint32_t page_offset;
     target_ulong vaddr;

--
2.14.1