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Re: [Qemu-devel] [PATCH v3] arm: implement cache/shareability attribute
From: |
Andrew Baumann |
Subject: |
Re: [Qemu-devel] [PATCH v3] arm: implement cache/shareability attribute bits for PAR registers |
Date: |
Tue, 31 Oct 2017 13:07:36 +0000 |
> From: Andrew Baumann
> Sent: Tuesday, 31 October 2017 21:02
[...]
> +static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
> +{
> + uint8_t hiattr = extract32(s2attrs, 2, 2);
> + uint8_t loattr = extract32(s2attrs, 0, 2);
> + uint8_t hihint = 0, lohint = 0;
> +
> + if (hiattr != 0) { /* normal memory */
> + /* TODO: to faithfully emulate S2CacheDisabled() for the case
> + * when EL2 is aarch32, we should check HCR2 (not HCR_EL2), but
> + * qemu doesn't presently model this register.
> + */
> + if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */
> + hiattr = loattr = 1; /* non-cacheable */
> + } else {
> + if (hiattr != 1) { /* Write-through or write-back */
> + hihint = 3; /* RW allocate */
> + }
> + if (loattr != 1) { /* Write-through or write-back */
> + lohint = 3; /* RW allocate */
> + }
> + }
> + }
> +
> + return (hiattr << 6) | (hihint << 2) | (loattr << 2) | lohint;
> +}
Right after sending this, I noticed a dumb copy-paste bug: the above should be
hihint << 4.
I'm obviously going a bit too fast, sorry.
Andrew