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[Qemu-devel] [PULL v2 2/5] target/openrisc: Make coreid and numcores var
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL v2 2/5] target/openrisc: Make coreid and numcores variable |
Date: |
Sat, 21 Oct 2017 07:05:30 +0900 |
Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.
Multicore support is now being added so these registers need to have
configured values.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/sys_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index abdef5d6a5..dc6e5cc7f2 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exception.h"
+#include "sysemu/sysemu.h"
#define TO_SPR(group, number) (((group) << 11) + (number))
@@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
return env->esr;
case TO_SPR(0, 128): /* COREID */
- return 0;
+ return cpu->parent_obj.cpu_index;
case TO_SPR(0, 129): /* NUMCORES */
- return 1;
+ return max_cpus;
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
idx = (spr - 1024);
--
2.13.6
- [Qemu-devel] [PULL v2 0/5] OpenRISC SMP Support, Stafford Horne, 2017/10/20
- [Qemu-devel] [PULL v2 2/5] target/openrisc: Make coreid and numcores variable,
Stafford Horne <=
- [Qemu-devel] [PULL v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC), Stafford Horne, 2017/10/20
- [Qemu-devel] [PULL v2 3/5] openrisc/cputimer: Perparation for Multicore, Stafford Horne, 2017/10/20
- [Qemu-devel] [PULL v2 4/5] openrisc: Initial SMP support, Stafford Horne, 2017/10/20
- [Qemu-devel] [PULL v2 5/5] openrisc: Only kick cpu on timeout, not on update, Stafford Horne, 2017/10/20
- Re: [Qemu-devel] [PULL v2 0/5] OpenRISC SMP Support, Peter Maydell, 2017/10/24