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Re: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) |
Date: |
Mon, 16 Oct 2017 13:10:18 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +/*
> + * do_reduction_op helper
> + *
> + * This mirrors the Reduce() pseudocode in the ARM ARM. It is
> + * important for correct NaN propagation that we do these
> + * operations in exactly the order specified by the pseudocode.
> + *
> + * This is a recursive function, TCG temps should be freed by the
> + * calling function once it is done with the values.
> + */
> +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
> + int esize, int size, int vmap, TCGv_ptr fpst)
> +{
> + if (esize == size) {
> + int element;
> + TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
> + TCGv_i32 tcg_elem;
> +
> + /* We should have one register left here */
> + assert(ctpop8(vmap) == 1);
I think you should match the ctpop to the size of vmap. It's true you only
need uint8_t at present, so maybe use that? At least it's self-consistent.
> + tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi,
> fpst);
> + tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo,
> fpst);
> + tcg_res = tcg_temp_new_i32();
You can re-use one of the two inputs for the output, fwiw.
> + /* Bit 1 of size field encodes min vs max and the actual size
> + * depends on the encoding of the U bit. If not set (and FP16
> + * enabled) then we do half-precision float instead of single
> + * precision.
> */
> is_min = extract32(size, 1, 1);
> is_fp = true;
> - size = 2;
> + if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> + size = 1;
You do still need to check size[0] == 0.
r~
- [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation, (continued)
- [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/10/13
- Re: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV),
Richard Henderson <=
- [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK), Alex Bennée, 2017/10/13