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Re: [Qemu-devel] [PATCH v2 2/5] target/openrisc: Make coreid and numcore
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable |
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Date: |
Fri, 13 Oct 2017 06:58:21 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 10/13/2017 06:49 AM, Stafford Horne wrote:
> Previously coreid and numcores were hard coded as 0 and 1 respectively
> as OpenRISC QEMU did not have multicore support.
>
> Multicore support is now being added so these registers need to have
> configured values.
>
> Signed-off-by: Stafford Horne <address@hidden>
> ---
> target/openrisc/sys_helper.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH v2 0/5] OpenRISC SMP Support, Stafford Horne, 2017/10/13
- [Qemu-devel] [PATCH v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC), Stafford Horne, 2017/10/13
- [Qemu-devel] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable, Stafford Horne, 2017/10/13
- Re: [Qemu-devel] [PATCH v2 2/5] target/openrisc: Make coreid and numcores variable,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 3/5] openrisc/cputimer: Perparation for Multicore, Stafford Horne, 2017/10/13
- [Qemu-devel] [PATCH v2 5/5] openrisc: Only kick cpu on timeout, not on update, Stafford Horne, 2017/10/13
- [Qemu-devel] [PATCH v2 4/5] openrisc: Initial SMP support, Stafford Horne, 2017/10/13