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[Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner ca
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner cases |
Date: |
Thu, 12 Oct 2017 17:03:34 +0100 |
The common situation of the SG instruction is that it is
executed from S&NSC memory by a CPU in NS state. That case
is handled by v7m_handle_execute_nsc(). However the instruction
also has defined behaviour in a couple of other cases:
* SG instruction in NS memory (behaves as a NOP)
* SG in S memory but CPU already secure (clears IT bits and
does nothing else)
* SG instruction in v8M without Security Extension (NOP)
These can be implemented in translate.c.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6634bad..4da1a4c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9778,7 +9778,28 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t
insn)
* - load/store doubleword, load/store exclusive, ldacq/strel,
* table branch.
*/
- if (insn & 0x01200000) {
+ if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) &&
+ arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* 0b1110_1001_0111_1111_1110_1001_0111_111
+ * - SG (v8M only)
+ * The bulk of the behaviour for this instruction is
implemented
+ * in v7m_handle_execute_nsc(), which deals with the insn when
+ * it is executed by a CPU in non-secure state from memory
+ * which is Secure & NonSecure-Callable.
+ * Here we only need to handle the remaining cases:
+ * * in NS memory (including the "security extension not
+ * implemented" case) : NOP
+ * * in S memory but CPU already secure (clear IT bits)
+ * We know that the attribute for the memory this insn is
+ * in must match the current CPU state, because otherwise
+ * get_phys_addr_pmsav8 would have generated an exception.
+ */
+ if (s->v8m_secure) {
+ /* Like the IT insn, we don't need to generate any code */
+ s->condexec_cond = 0;
+ s->condexec_mask = 0;
+ }
+ } else if (insn & 0x01200000) {
/* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
* - load/store dual (post-indexed)
* 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
--
2.7.4
- [Qemu-devel] [PULL 06/13] target/arm: Implement secure function return, (continued)
- [Qemu-devel] [PULL 06/13] target/arm: Implement secure function return, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 01/13] watchdog/aspeed: fix variable type to store reload value, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 09/13] target-arm: Simplify insn_crosses_page(), Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 03/13] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index(), Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 12/13] nvic: Add missing 'break', Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 13/13] nvic: Fix miscalculation of offsets into ITNS array, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 08/13] target/arm: Pull Thumb insn word loads up to top level, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 02/13] arm: fix armv7m_init() declaration to match definition, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 05/13] target/arm: Implement BLXNS, Peter Maydell, 2017/10/12
- [Qemu-devel] [PULL 11/13] target/arm: Implement SG instruction corner cases,
Peter Maydell <=
- [Qemu-devel] [PULL 10/13] target/arm: Support some Thumb insns being always unconditional, Peter Maydell, 2017/10/12
- Re: [Qemu-devel] [PULL 00/13] target-arm queue, Peter Maydell, 2017/10/16