Re: [Qemu-devel] [PATCH v4] target/ppc: Fix carry flag setting for shift algebraic instructions

[Richard Henderson]

On 10/06/2017 01:40 AM, Sandipan Das wrote:
> For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
> right algebraic instructions whenever the CA bit is to be set. This
> change affects the following instructions:
>   * Shift Right Algebraic Word (sraw[.])
>   * Shift Right Algebraic Word Immediate (srawi[.])
>   * Shift Right Algebraic Doubleword (srad[.])
>   * Shift Right Algebraic Doubleword Immediate (sradi[.])
> 
> Signed-off-by: Sandipan Das <address@hidden>
> ---
> v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()
> 
> v3: Remove explicit checking for ISA v3.0 when setting CA32
> 
> v4: Set CA32 only when CA is being modified (as Richard suggested)
>     Set CA32 after checking for ISA300 in gen_* functions (as David suggested)
> ---
>  target/ppc/int_helper.c | 16 ++++++++--------
>  target/ppc/translate.c  | 12 ++++++++++++
>  2 files changed, 20 insertions(+), 8 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


r~