Re: [Qemu-devel] [PATCH] sun4u: update PCI topology to include simba PCI

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Re: [Qemu-devel] [PATCH] sun4u: update PCI topology to include simba PCI

From:	Artyom Tarasenko
Subject:	Re: [Qemu-devel] [PATCH] sun4u: update PCI topology to include simba PCI bridges
Date:	Wed, 27 Sep 2017 14:09:23 +0200
On Wed, Sep 27, 2017 at 8:45 AM, Mark Cave-Ayland
<address@hidden> wrote:
> This patch updates the sun4u model to being much closer to a real Ultra 5
> by moving devices behind the 2 simba PCI bridges (A and B) as found on real
> hardware.
>
> The most noticeable change introduced by this patchset is that in-built 
> devices
> are no longer attached to the PCI root bus, but instead behind PCI bridge A.
> Along with this the interrupt routing is updated accordingly to match the
> official documentation.
>
> Since the existing code currently bypasses the PCI bridge interrupt
> swizzling, the interrupt mapping functions are reorganised so that
> pci_pbm_map_irq() is used by the PCI bridges and pci_apb_map_irq() is
> used by the PCI host bridge.
>
> Behind the sabre PCI host bridge, the PCI IO space now needs to be
> split into two separate halves at 0x8000000. Therefore we also setup a new
> PCI IO space region of increased size on the PCI host bridge and enable
> 32-bit PCI IO accesses to allow IO accesses to reach devices behind PCI
> bridge B correctly.
>
> As part of this change we also combine the onboard sunhme NIC and the ebus
> into a single multi-function device as done on a real Ultra 5. For other
> NICs we initialise them and place them into the next free slot on PCI
> bus B.
>
> Finally we mark the physically unavailable slots (plus slot 0 in busA) as
> reserved to ensure that users can't plug devices into non-existent slots
> which will break interrupt routing.
>
> Note: since this commit changes PCI topology and interrupt routing, an
> updated openbios-sparc64 binary is included with this commit containing the
> associated changes to maintain bisectability.
>
> Signed-off-by: Mark Cave-Ayland <address@hidden>

Reviewed-by: Artyom Tarasenko <address@hidden>

> ---
>  hw/pci-host/apb.c        |   47 +++++++++++++++++++++++++++---------
>  hw/sparc64/sun4u.c       |   60 
> +++++++++++++++++++++++++++++++++-------------
>  pc-bios/openbios-sparc64 |  Bin 1593408 -> 1593408 bytes
>  3 files changed, 79 insertions(+), 28 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index b709456..bc54366 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -599,16 +599,35 @@ static uint64_t apb_pci_config_read(void *opaque, 
> hwaddr addr,
>  /* The APB host has an IRQ line for each IRQ line of each slot.  */
>  static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
>  {
> -    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
> +    /* Return the irq as swizzled by the PBM */
> +    return irq_num;
>  }
>
>  static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
>  {
> +    PBMPCIBridge *br = PBM_PCI_BRIDGE(pci_bridge_get_device(
> +                           PCI_BUS(qdev_get_parent_bus(DEVICE(pci_dev)))));
> +
>      int bus_offset;
> -    if (pci_dev->devfn & 1)
> -        bus_offset = 16;
> -    else
> -        bus_offset = 0;
> +    if (br->busA) {
> +        bus_offset = 0x0;
> +
> +        /* The on-board devices have fixed (legacy) OBIO intnos */
> +        switch (PCI_SLOT(pci_dev->devfn)) {
> +        case 1:
> +            /* Onboard NIC */
> +            return 0x21;
> +        case 3:
> +            /* Onboard IDE */
> +            return 0x20;
> +
> +        default:
> +            /* Normal intno, fall through */
> +            break;
> +        }
> +    } else {
> +        bus_offset = 0x10;
> +    }
>      return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
>  }
>
> @@ -669,6 +688,12 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error 
> **errp)
>                   PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
>                   PCI_STATUS_DEVSEL_MEDIUM);
>
> +    /* Allow 32-bit IO addresses */
> +    pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
> +    pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
> +    pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
> +    pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
> +
>      pci_bridge_update_mappings(PCI_BRIDGE(br));
>  }
>
> @@ -690,9 +715,9 @@ PCIBus *pci_apb_init(hwaddr special_base,
>      d = APB_DEVICE(dev);
>      phb = PCI_HOST_BRIDGE(dev);
>      phb->bus = pci_register_bus(DEVICE(phb), "pci",
> -                                pci_apb_set_irq, pci_pbm_map_irq, d,
> +                                pci_apb_set_irq, pci_apb_map_irq, d,
>                                  &d->pci_mmio,
> -                                get_system_io(),
> +                                &d->pci_ioport,
>                                  0, 32, TYPE_PCI_BUS);
>      qdev_init_nofail(dev);
>      s = SYS_BUS_DEVICE(dev);
> @@ -725,14 +750,14 @@ PCIBus *pci_apb_init(hwaddr special_base,
>      pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
>                                     TYPE_PBM_PCI_BRIDGE);
>      br = PCI_BRIDGE(pci_dev);
> -    pci_bridge_map_irq(br, "pciB", pci_apb_map_irq);
> +    pci_bridge_map_irq(br, "pciB", pci_pbm_map_irq);
>      qdev_init_nofail(&pci_dev->qdev);
>      *busB = pci_bridge_get_sec_bus(br);
>
>      pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
>                                     TYPE_PBM_PCI_BRIDGE);
>      br = PCI_BRIDGE(pci_dev);
> -    pci_bridge_map_irq(br, "pciA", pci_apb_map_irq);
> +    pci_bridge_map_irq(br, "pciA", pci_pbm_map_irq);
>      qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
>      qdev_init_nofail(&pci_dev->qdev);
>      *busA = pci_bridge_get_sec_bus(br);
> @@ -798,8 +823,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
>      sysbus_init_mmio(dev, &s->pci_config);
>
>      /* pci_ioport */
> -    memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
> -                             get_system_io(), 0, 0x10000);
> +    memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 
> 0x1000000);
> +
>      /* at region 2 */
>      sysbus_init_mmio(dev, &s->pci_ioport);
>
> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
> index c3280aa..2edd1cc 100644
> --- a/hw/sparc64/sun4u.c
> +++ b/hw/sparc64/sun4u.c
> @@ -27,6 +27,7 @@
>  #include "cpu.h"
>  #include "hw/hw.h"
>  #include "hw/pci/pci.h"
> +#include "hw/pci/pci_bus.h"
>  #include "hw/pci-host/apb.h"
>  #include "hw/i386/pc.h"
>  #include "hw/char/serial.h"
> @@ -42,6 +43,7 @@
>  #include "hw/nvram/fw_cfg.h"
>  #include "hw/sysbus.h"
>  #include "hw/ide.h"
> +#include "hw/ide/pci.h"
>  #include "hw/loader.h"
>  #include "elf.h"
>  #include "qemu/cutils.h"
> @@ -436,7 +438,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>      DeviceState *dev;
>      FWCfgState *fw_cfg;
>      NICInfo *nd;
> -    int onboard_nic_idx;
> +    MACAddr macaddr;
> +    bool onboard_nic;
>
>      /* init CPUs */
>      cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model,
> @@ -450,10 +453,17 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>      ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX);
>      pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, 
> &pci_busA,
>                             &pci_busB, &pbm_irqs);
> -    pci_vga_init(pci_bus);
>
> -    /* XXX Should be pci_busA */
> -    ebus = pci_create_simple(pci_bus, -1, "ebus");
> +    /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
> +       reserved (leaving no slots free after on-board devices) however slots
> +       0-3 are free on busB */
> +    pci_bus->slot_reserved_mask = 0xfffffffc;
> +    pci_busA->slot_reserved_mask = 0xfffffff1;
> +    pci_busB->slot_reserved_mask = 0xfffffff0;
> +
> +    ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, "ebus");
> +    qdev_init_nofail(DEVICE(ebus));
> +
>      isa_bus = pci_ebus_init(ebus, pbm_irqs);
>
>      i = 0;
> @@ -466,27 +476,43 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>      serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS);
>      parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
>
> -    onboard_nic_idx = -1;
> +    pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
> +
> +    memset(&macaddr, 0, sizeof(MACAddr));
> +    onboard_nic = false;
>      for (i = 0; i < nb_nics; i++) {
>          nd = &nd_table[i];
>
> -        if (onboard_nic_idx == -1 &&
> -                (!nd->model || strcmp(nd->model, "sunhme") == 0)) {
> -            pci_dev = pci_create(pci_bus, -1, "sunhme");
> -            dev = &pci_dev->qdev;
> -            qdev_set_nic_properties(dev, nd);
> -            qdev_init_nofail(dev);
> -
> -            onboard_nic_idx = i;
> +        if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
> +            if (!onboard_nic) {
> +                pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
> +                                                   true, "sunhme");
> +                memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
> +                onboard_nic = true;
> +            } else {
> +                pci_dev = pci_create_simple(pci_busB, -1, "sunhme");
> +            }
>          } else {
> -            pci_nic_init_nofail(nd, pci_bus, "ne2k_pci", NULL);
> +            pci_dev = pci_create_simple(pci_busB, -1, nd->model);
>          }
> +
> +        dev = &pci_dev->qdev;
> +        qdev_set_nic_properties(dev, nd);
> +        qdev_init_nofail(dev);
> +    }
> +
> +    /* If we don't have an onboard NIC, grab a default MAC address so that
> +     * we have a valid machine id */
> +    if (!onboard_nic) {
> +        qemu_macaddr_default_if_unset(&macaddr);
>      }
> -    onboard_nic_idx = MAX(onboard_nic_idx, 0);
>
>      ide_drive_get(hd, ARRAY_SIZE(hd));
>
> -    pci_cmd646_ide_init(pci_bus, hd, 1);
> +    pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
> +    qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
> +    qdev_init_nofail(&pci_dev->qdev);
> +    pci_ide_create_devs(pci_dev, hd);
>
>      isa_create_simple(isa_bus, "i8042");
>
> @@ -527,7 +553,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>                             /* XXX: need an option to load a NVRAM image */
>                             0,
>                             graphic_width, graphic_height, graphic_depth,
> -                           (uint8_t *)&nd_table[onboard_nic_idx].macaddr);
> +                           (uint8_t *)&macaddr);
>
>      dev = qdev_create(NULL, TYPE_FW_CFG_IO);
>      qdev_prop_set_bit(dev, "dma_enabled", false);
> diff --git a/pc-bios/openbios-sparc64 b/pc-bios/openbios-sparc64
> index 
> 7bdd6a1f4977eae6693883468cab78ba3ba363cf..955f45d33238dda2f1e99d97be9463fd1fac479d
>  100644
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> zinHaHc2Ekb(ALJ50UlKhkAYKa=C8>c4VD&LG>)#7Ex+_pVS<nx?JEi&!T^yV^kkFB
> z2Mjw&p#&iz+K-G!sEJ8Pj`8!VkQ_q2OhV7-fw1rZ<(address@hidden;vq}x^{qJ`
> zbE1$L#a58LjWABqjpX3Hx-nSE*;eR4;Wk2(XqVaxVp|~-+XmLQkYN!$-WGk5RIB_?
> zY;>xv(3ef1mPye4aIz)|&r8X*9=UZVh^y&xk}x}(xN~~uBnw}%=(c#bdd9aCb~lKb
> zuQ|X!hS3cvLT76J1I+j1_sN!m=Df+(tqJu`3WVwocExls1$`E#%PFuPGdWX*mPV|O
> znm;bSWTk<rLMvf?8OO#8>(6`2QU&ayJx)VA3Vox0fp)6M)>~+~%Ko*{v!SDKXJgD~
> zL%q<t=jevsLMrRz8QNP&7ot}~!aR?ouP~WK_s6?~sxr{h;address@hidden|i
> zw&C%lYv!*lBC!Yyb+IVCuM_R)address@hidden@address@hidden)9o-bAH5
> z)s2qv)D3jGKl-^1wHY9!M~fJRoFxN<*33xx1B6r_ICC5n;Fw=&2Qb(II5hwTzM{(<
> zIH}D*p=ZotR0`wS|0ZP*6gsd`^yom4-bovfiM=ZSK<IBh8E-;rH4VH8d4p&Q2M$`w
> zk+aFmQ)N_jlaL<ssMbMyo0Bp~=-ku_=6SF>OhNWC${qxI3oRXl+RxKwp6X12K|*R`
> zJIHF{%5fqPujph}un~eO!k)address@hidden>Hin_Uv-T
> z2c3F2Kdy!INmqsQJ^!K&nL=lFfqa=z$XYtj`39(oMQGjh6U^PqwMovNr>K`j=$ZHt
> address@hidden
> zHr$L}odF#bLI+rP?`cElZwB{qKovjH&8_s#{8iauaPX{HXS~Zx8MmO|5X!p+D$OM4
> zEkXkOp2~PCoqPZtZ-kY*i^3nA;N)Bv7`~2keK_OV`<{SKRvP#SxTiHKw?eU)zt~)R
> zCT^PNjIU8FMvxD7lkHX^N!Sxbj$5IYYR~3dg>gdkk7#y<r^)address@hidden
> zU?DT^wBDVV8ejPu_RQsem%3yj{)|V-YO-btecOHjs_Trp-dVIE3*8R8%F^s=2%1J@
> z9)i@<WaFuYR6GO>AI1vJppE<address@hidden;k>TD$vq
> zHqvttxdI~4`JrI?Ew#BzI82A{65<+wMD#Qm2A7R7X+iG&V>HmJMut+W(6i|ZZN~fZ
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> z<ah~(1r|foMVPY}g*UI{4s>*)1w-^3Z<10f%!<#c)@d4Z8a>ZR8%hO=E7Y^pBLzJx
> zm#ohU<Km2ek~M_9JgfLmvbvJ_IpI0sjfQmaIpF{%6|0}eFu9Y&wZf{HW4?)eb>MuK
> zHm?=JtkARh1))P!bSC=9M8{l0hv?pTwRtYPge48wc+can2)7zpsi)!%A-w^c=&62F
> zxQDUWB}2Ch_>00{1N=qfuc2q?_C`CGu5h;TFpIH6BSA5EQU)74HfIe;8Es7O-T-EA
> z2>address@hidden;ds#w`662}<l3R|nFc#QFO4t-;cgK7C><0wyl
> zw(<8EmgUKtWZc?<Z6L=J#*vgi*Eo)4lXJ4sN~U?nd3<APo^dcs(@<%J#wD;QcOg(M
> zsagY;hmFgT@;address@hidden;ZZnyaQ_`lnAek5Wb_D_&j%JFyModd0Th#+1Fxri
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> zuE<{$;4O(f;Ul}%*IFBTZ*wG%!|;*!bd8Oy(address@hidden&>address@hidden|?t=y6K
> z#_Q>74o8CFKn)RLc<Nm}tus93(9#ix!Si}rXL#}}J*_efA31rET*bz-?OYl<BG<)I
> address@hidden<2b~M_g(`#}cjn?QQ?K;Xw6z*Gk`J>UQUXT`5{Lu#GT7JG$
> zOUoMc>&-eUUexk+d5(&!)pSt}!{#?=1ovx#9BuKao_474XmgjIwrFWlSLDJ%J+0yW
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> z)X{-?JRNz$M+Zh2dO0q9bZC|aM;bMF*ILRPYmE1tdD{43&n33qM*PL#FBX4|@z(@@
> zP4U;vW82-_<yheqcUi>address@hidden
> z_Ld**N%*_CI+kbe^K4xr4rD5&=R&dg^X%x(D^ld`o^zK)X9E`S6f$X!(6mQyrH8qD
> zU!{AW{=Iv8ev6XiI9_BwHBXd$tjZHel){~GDi^p-TG*Ig-6gk)3O4tX?H4hD3S43{
> zqym&}l~M$;kQ`Pi9r4F)m8P+34w5M|UN%zZ2q_DDF2y4xoa>a_EzK3=EVAD(CJ_=6
> zwz*w*N(r?4Zpny%WPTFG(ocwu=!d(address@hidden(Je
> z;;m9VExQNYO38H(#PE`jgVK_bQeQ69eR482KO~A&@address@hidden&(9%T3Bc*l7b>zuO
> zwCo*-I&74bBl)yS)KT3K4z^UtI|?%R$vZ;address@hidden>o
> z+Q>CpI*cP-`xt3B&C8ZdbYhIOPB0nCI|hwho-LUnn>SnPCL|g?p=_z4AS7l`V6qq&
> z6-=~{I8I8Eaq6l)e8K?<61-#?C#8aW-Z(V3kZjXX`HSPEw}8qXj~pL4IH(}&KgCo!
> zJYH%fv`t>IP@(address@hidden)q|syqhLS={4%s
> z#Xz~xx2Sm51nJ=j`4y0B3JV7ssP%+{pwk&EMPeM?HBo9WIdu`Vo~!HzYnceiRPRET
> z-l2*}&OgvK$pP|Cgo+d+g(gD8DiUo#D;YeQK$$kln5cPjz+lR^=jP6M!r<UFgoBEm
> zY&Nxs!-fjVI2MmyK|8$y1r^v(K|55SQHwdKpdBheDay>bwt|8gxiuBELj^fn1vyY#
> z8I|%>fXZ{EB%!^5{3?XzRcIm8BxKttg98VJmZN`)CP}5trM+iPmR!gVOok8LkVeKS
> address@hidden;address@hidden>!4z~?HkD0*cNEqs<{(Qy^ym+q#6i_l
> zq(Q=sBH5;(*sxqF5xBfu7>%2p9QbiT0F|U*izgSFNl7DdDqL~NRH-=)nku!c%Rbpl
> address@hidden(zkQ>address@hidden|n2>5BWtudc<address@hidden<=(wkcO;>LEbG-^%iR$
> zv{Fj;address@hidden;mzHqOGBU-_-41*STAo{I4JtaJzcs0wCjF&w~c)FqkI*G
> z?nlAS8Ql66%9sJEY-F9m{hu5&qyqq|address@hidden<@f`&2+6nSLj0E8SMQg8s5
> zm<1iALk9(*%_eJ0SjEHw2}>Swa1=a^qYf8H$%5HHp#qSbGf1&(EI9y6yXuqfo=`%w
> zXT?TQ!E^)p?9ylfP<etI+5^%wo+x`jDxl;cQj$vIo`d!edk_l6*3^S)H1*DrQmOfD
> zDFZE2hDdE&1bgJEItie9RX6FSR5%+-SBoT5@(~2Pb)O=RUYU))wo!=pQnxvhgV%=|
> z3b+Oy;%%5K-AsiKL6MjVgLM>address@hidden|VTqinp;8?)ZI
> z(gdNefz0!umO}DHfo0J=XbN$C9+)_&Vjg(address@hidden@DB
> z7Zf6RmXiBn^q`%r3&a%q;bGK<Hr))BOn5}<hj;Nb-nTpg_1G!!2ztJ+k!(L<I7yi=
> zWeFK(vd@>M3T6xW=SzJ!6dy%*xXAJ-B!mTV?Jj$iE5%dxC`1FBioZir7~tR4uDxnJ
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> zJ%(1G-s;C-u!xb5!*aajeq0(P53*?dBBq*YDtQ8WhhCq6?ZB>}6)uGeR2}i|S5<|~
> zz!TB}m1wc*R8D9~$jBh~Vu%bFSS*b}MWL{mOv6cTM)&O#V`$bADeX_{rLraHod6dH
> zk3O!MeN?>address@hidden&+){<PH4N+Kw31t4$rp;H
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> zWf;V~_0V2UU0n|address@hidden)vZpV!IJ-g?yKK(i3}m!sKMg^W%p4wFnL
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> zw+60=X(&>3Vhu{!*GP?M-5N>cL4jjaOMvxq?1eQDVYE_GBBjvW5-_}}M3UiO))J5%
> z;ACQn6iv?nOXqmf4I+%`$j8B8i4;q>6PKU_emDkq#t2p0D2pJ7lk5a%IZKjhh0{n|
> z3G<@address@hidden
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> zh?eU6OY5b!&=qL<2$PH&PJT&address@hidden|!ji+KF?78I^HBX7eW}lC
> zS6Zp!C0NsBy`Ll2WWz8r1zK$Kveb!6UY44-4&address@hidden)CfXfzl*3f
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> address@hidden@address@hidden(MPH}&}V9PZJ$ln45p?JN8y&_8!+_A8Dx81>KkK?up`F?
> zDZc%TY>gfBsW3R&rKKY#pcQLNzq~HVLjpVxkFJfnW$UI#IXE#ybg8gLB=EFumd4aw
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> zC6O9##r$Se206BZ2uq2rP)address@hidden(Ps-RqEEiz{0uX(G`BZM*TZQ52#g{
> zi?f1l{D*Cskw(RCxV7EF%i+<bfcRcFTn00yrF`lOBMP~tcv*Lg;3z*Q<{e3<H&x>a
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> z;UgTiHv<RNRjl}lno>8AF3b~~(address@hidden|address@hidden>FQeQ1_
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> z5X}N=(address@hidden|address@hidden>y<dJ9%Y1%qZ8rI+|QIF66S~SamxuQ
> zog+mmI)PS|sde%UE&>(!Fag%<J#<3lBKjd=dHw8J{)pRkMK>2x$d7KWFOcnXY_wvj
> address@hidden;|N!fq&amv!fl+7cF4ZI)N06@@U_&a
> zF$OQKK_d}b(0tDFB;V-BBJ(yG8d#Y{)address@hidden)+!V@
> zg`R=6oaVh;vWU;CB^(^^q=5=g<K(C|88{6yc_EF`&Y(~28qWo1u)F$#nQyu$dp4bc
> address@hidden|pH*!DXP(8d%na0CwwLMluHBN$V9ZJ05+*WVc9`AdIpQU!6kM
> z1wm;AVx(9Jl$$atF$y7Kww2;N?^nX6v2M1l=8F9iXI9l7<twQV6E>JV+5g0;6*|!W
> address@hidden&3IMRHZwB6kt}G7;~V5xkoy~)address@hidden
> zn3l)I3kP2<address@hidden)address@hidden(M#kg`{aQ
> zHS$t<2-^U)$?A}lSyYpZ6#D-b7Dd#V;@2upRdi_Ap;v<uy8jlY>3q@@jo+|R6{25V
> z8Y05DQ%Fn4>oCEqrL8Uvw$=r;`m}VU+<ylfgo7gtRQ{7RD0W1e#&CqS<Yy^<Z0js7
> znJa2=s$GZG8f>V;6t|X6G3(H#!4VEUt-~91c%up5Wk?A{HUpk;address@hidden&C{;OuR
> zcBpiLurA(T(O)mWrsJ<address@hidden|x2WRg=e87kK_r%#H4ql{WwpBw~-^CUDK3C}qu
> zp1zHblUhbjp$^M*=-1#RQHMI+B%N-OPB#fx1%Hu}iu7%>;OM{T!pX%NzsXe^jI81H
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> address@hidden;RCaK){q+v)address@hidden>pU
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> z9M8UIA>|MCxKN$FzyF7n6H};heh({!d`#5`U6GXbubLuA4Zfxk)okg$mqm^%SbJ1c
> address@hidden@address@hidden|vbEc}V&QEK!j;>y
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> z$hQl7a1}z3lQrJq${CtO!Tnhpuf0|s>doBCn+e{Lx^>=_9zRuqjdo5O4(_$<#c=sC
> address@hidden&{Fn39{Xy+g<Q6#fcmq%stXvFS+*1)address@hidden|k
> zcIYsh(address@hidden<B*EGmnZo9ml;!4DO!
> z<o;@^h>oaE<${00!2@|(_J;u-R_M^DF^*KMF)nT>H<J&D8p#0;xNLqZYbYnl2P|6p
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> z2S!x++C}*S_8DxFJPjKY{QjZmj3ir`d{i}^T8W0>Af$y{gvz}wz}{aH!cIuIg>2N0
> z=flBIpp%yJufkDm^5N#9CnZjv&address@hidden;7oE6VQF$vtrxE!NWTKQwJ#t
> zh)O3cJR^xlC&=v}qjNsCwznR|zUiUPxIw=qL4Fo`#9l}eO*P3wpcc1DPS9dQt)vHi
> zWRY<vfB1daFKd)2UlKkSOIkrwUto`{6<VD~77n0P4$8>EK?S)us3I>XJ!zzX3e!qj
> address@hidden(Brb_y4K+8{TZ%pBl|uMN86KpR=2;x<qL
> address@hidden
> zNub102?y2WOG4FWVcbdJa~44|8Fkpml8jtPoh*AGwMo&C928R?2X1mIa4SFg6)address@hidden
> zCGF4~!89_pgK-8`U#(address@hidden)cU3#`#k>lu-cCt)M(q!xmPRFJ-K5U4g
> za635zmYUICJ`k~=AllLaQ6r^;oD<n&3|cv^D6);qlQ&?4HvI<KhSGSSr-1}YzEQT&
> z*)+LfR1j2oHzJs6QHv)n<DjoCH_G?cQiv&NwU*-<mLg{eLS-7+z5v~eX|hGAG<yPR
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>
> --
> 1.7.10.4
>



-- 
Regards,
Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
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[Qemu-devel] [PATCH] sun4u: update PCI topology to include simba PCI bridges, Mark Cave-Ayland, 2017/09/27
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