Re: [Qemu-devel] [RFC PATCH v2 14/21] ppc/xive: add support for the SET_OS_PENDING command

[Cédric Le Goater]

On 09/19/2017 09:55 AM, David Gibson wrote:
> On Mon, Sep 11, 2017 at 07:12:28PM +0200, Cédric Le Goater wrote:
>> Adjusting the Interrupt Pending Buffer for the O/S would allow a CPU
>> to process event queues of other priorities during one physical
>> interrupt cycle. This is not currently used by the XIVE support for
>> sPAPR in Linux but it is by the hypervisor.
>>
>> Signed-off-by: Cédric Le Goater <address@hidden>
>> ---
>>  hw/intc/spapr_xive.c | 9 ++++++++-
>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
>> index ad3ff91b13ea..ad3f03e37401 100644
>> --- a/hw/intc/spapr_xive.c
>> +++ b/hw/intc/spapr_xive.c
>> @@ -162,7 +162,14 @@ static bool spapr_xive_tm_is_readonly(uint8_t index)
>>  static void spapr_xive_tm_write_special(ICPState *icp, hwaddr offset,
>>                                    uint64_t value, unsigned size)
>>  {
>> -    /* TODO: support TM_SPC_SET_OS_PENDING */
>> +    if (offset == TM_SPC_SET_OS_PENDING && size == 1) {
>> +        icp->tima_os[TM_IPB] |= priority_to_ipb(value & 0xff);
>> +        icp->tima_os[TM_PIPR] = ipb_to_pipr(icp->tima_os[TM_IPB]);
> 
> This only lets the cpu raise bits in the IPB, never clear them.> Is that 
> right?  

The clear is done when the OS acks the interrupt.

> I don't see how you'd implement the handling of multiple
> priorities without being able to clear bits here.

I am not sure how this command should be used from the OS. 
Currently, I only see KVM handling it in the XICS/XIVE glue.
I need to take a closer look.

C.
 


>> +        spapr_xive_icp_notify(icp);
>> +    } else {
>> +        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid TIMA write @%"
>> +                      HWADDR_PRIx" size %d\n", offset, size);
>> +    }
>>  
>>      /* TODO: support TM_SPC_ACK_OS_EL */
>>  }
>