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[Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing |
Date: |
Thu, 14 Sep 2017 18:52:52 +0100 |
From: Pranavkumar Sawargaonkar <address@hidden>
Now we are able to retrieve the gsi from the INTx pin, let's
enable intx_to_irq routing. From that point on, irqfd becomes
usable along with INTx when assigning a PCIe device.
Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Tushar Jagad <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Tested-by: Feng Kan <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/pci-host/gpex.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index 41a884d..be25245 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -53,6 +53,17 @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
return 0;
}
+static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
+{
+ PCIINTxRoute route;
+ GPEXHost *s = opaque;
+
+ route.mode = PCI_INTX_ENABLED;
+ route.irq = s->irq_num[pin];
+
+ return route;
+}
+
static void gpex_host_realize(DeviceState *dev, Error **errp)
{
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
@@ -77,6 +88,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
&s->io_ioport, 0, 4, TYPE_PCIE_BUS);
qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
+ pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
qdev_init_nofail(DEVICE(&s->gpex_root));
}
--
2.7.4
- [Qemu-devel] [PULL 00/18] target-arm queue, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 13/18] AArch64: Fix single stepping of ERET instruction, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 15/18] hw/pci-host/gpex: Set INTx index/gsi mapping, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 16/18] hw/arm/virt: Set INTx/gsi mapping, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing,
Peter Maydell <=
- [Qemu-devel] [PULL 14/18] target/arm: Avoid an extra temporary for store_exclusive, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 08/18] xlnx-ep108: Rename to ZCU102, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 03/18] target/arm: Get PRECISERR and IBUSERR the right way round, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 06/18] target/arm: Add and use defines for EXCRET constants, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 04/18] nvic: Don't apply group priority mask to negative priorities, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 07/18] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit(), Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 05/18] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit(), Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 02/18] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 11/18] xlnx-zcu102: Add a machine level virtualization property, Peter Maydell, 2017/09/14
- [Qemu-devel] [PULL 12/18] xlnx-zcu102: Mark the EP108 machine as deprecated, Peter Maydell, 2017/09/14