Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers

[Richard Henderson]

On 09/12/2017 11:50 AM, Philippe Mathieu-Daudé wrote:
>>
>> -        float64 regs[64];
>> +        float64 regs[64] __attribute__((aligned(16)));
> 
> I understand this should be aligned to the biggest vector register the host
> support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it correct?

No.

Alignment of 16 is sufficient for "older" vector extensions, like altivec,
which require alignment in load/store insns.  But (so far at least) newer
vector extensions with larger vector sizes (AVX2, AVX512, ARM SVE) handle
unaligned load/store operations just fine.

Which means we need not require excessive alignment within the cpu struct.

The rule for this is documented in tcg/tcg-op-gvec.h, iirc.


r~