[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK register banked for v
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK register banked for v8M |
Date: |
Thu, 7 Sep 2017 14:28:07 +0100 |
Make the PRIMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to
be restricted).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 2 +-
hw/intc/armv7m_nvic.c | 2 +-
target/arm/helper.c | 4 ++--
target/arm/machine.c | 9 +++++++--
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 273abc3..26ec744 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -431,7 +431,7 @@ typedef struct CPUARMState {
uint32_t bfar; /* BusFault Address */
unsigned mpu_ctrl; /* MPU_CTRL */
int exception;
- uint32_t primask;
+ uint32_t primask[2];
uint32_t faultmask;
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
} v7m;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 2a41e5d..a654792 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -169,7 +169,7 @@ static inline int nvic_exec_prio(NVICState *s)
if (env->v7m.faultmask) {
running = -1;
- } else if (env->v7m.primask) {
+ } else if (env->v7m.primask[env->v7m.secure]) {
running = 0;
} else if (env->v7m.basepri[env->v7m.secure] > 0) {
running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7007266..9a7ab96 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8830,7 +8830,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
env->regs[13] : env->v7m.other_sp;
case 16: /* PRIMASK */
- return env->v7m.primask;
+ return env->v7m.primask[env->v7m.secure];
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
return env->v7m.basepri[env->v7m.secure];
@@ -8890,7 +8890,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg,
uint32_t val)
}
break;
case 16: /* PRIMASK */
- env->v7m.primask = val & 1;
+ env->v7m.primask[env->v7m.secure] = val & 1;
break;
case 17: /* BASEPRI */
env->v7m.basepri[env->v7m.secure] = val & 0xff;
diff --git a/target/arm/machine.c b/target/arm/machine.c
index dbb432d..3c42bf5 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -103,7 +103,7 @@ static const VMStateDescription vmstate_m_faultmask_primask
= {
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.faultmask, ARMCPU),
- VMSTATE_UINT32(env.v7m.primask, ARMCPU),
+ VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
VMSTATE_END_OF_LIST()
}
};
@@ -251,6 +251,7 @@ static const VMStateDescription vmstate_m_security = {
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.secure, ARMCPU),
VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
+ VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST()
}
};
@@ -271,9 +272,13 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
* differences are that the T bit is not in the same place, the
* primask/faultmask info may be in the CPSR I and F bits, and
* we do not want the mode bits.
+ * We know that this cleanup happened before v8M, so there
+ * is no complication with banked primask/faultmask.
*/
uint32_t newval = val;
+ assert(!arm_feature(env, ARM_FEATURE_M_SECURITY));
+
newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);
if (val & CPSR_T) {
newval |= XPSR_T;
@@ -287,7 +292,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
env->v7m.faultmask = 1;
}
if (val & CPSR_I) {
- env->v7m.primask = 1;
+ env->v7m.primask[M_REG_NS] = 1;
}
val = newval;
}
--
2.7.4
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 15/31] target/arm: Make FAULTMASK register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK register banked for v8M,
Peter Maydell <=
- [Qemu-devel] [PULL 01/31] armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 18/31] target/arm: Make VTOR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 13/31] target/arm: Make BASEPRI register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 12/31] target/arm: Add MMU indexes for secure v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 11/31] target/arm: Register second AddressSpace for secure v8M CPUs, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 07/31] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 10/31] target/arm: Add state field, feature bit and migration for v8M secure state, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 04/31] xlnx_zynqmp: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 09/31] target/arm: Implement new PMSAv8 behaviour, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 20/31] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M, Peter Maydell, 2017/09/07