[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 17/32] target/arm: [tcg, a64] Port to init_disas_cont
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 17/32] target/arm: [tcg, a64] Port to init_disas_context |
Date: |
Wed, 6 Sep 2017 09:05:57 -0700 |
From: Lluís Vilanova <address@hidden>
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Benneé <address@hidden>
Message-Id: <address@hidden>
[rth: Adjust for max_insns interface change.]
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 38 ++++++++++++++++++++++++--------------
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f5c678ef25..e8dc96c28a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env,
DisasContext *s)
free_tmp_a64(s);
}
-void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
- TranslationBlock *tb)
+static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
+ CPUState *cpu, int max_insns)
{
- CPUARMState *env = cs->env_ptr;
- ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext *dc = container_of(dcbase, DisasContext, base);
- target_ulong next_page_start;
- int max_insns;
-
- dc->base.tb = tb;
- dc->base.pc_first = dc->base.tb->pc;
- dc->base.pc_next = dc->base.pc_first;
- dc->base.is_jmp = DISAS_NEXT;
- dc->base.num_insns = 0;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
+ CPUARMState *env = cpu->env_ptr;
+ ARMCPU *arm_cpu = arm_env_get_cpu(env);
dc->pc = dc->base.pc_first;
dc->condjmp = 0;
@@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
dc->vec_len = 0;
dc->vec_stride = 0;
- dc->cp_regs = cpu->cp_regs;
+ dc->cp_regs = arm_cpu->cp_regs;
dc->features = env->features;
/* Single step state. The code-generation logic here is:
@@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
init_tmp_a64_array(dc);
+ return max_insns;
+}
+
+void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
+ TranslationBlock *tb)
+{
+ CPUARMState *env = cs->env_ptr;
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ target_ulong next_page_start;
+ int max_insns;
+
+ dc->base.tb = tb;
+ dc->base.pc_first = dc->base.tb->pc;
+ dc->base.pc_next = dc->base.pc_first;
+ dc->base.is_jmp = DISAS_NEXT;
+ dc->base.num_insns = 0;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+
next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) +
TARGET_PAGE_SIZE;
max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
@@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
+ max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);
gen_tb_start(tb);
--
2.13.5
- [Qemu-devel] [PULL 14/32] target/i386: [tcg] Port to generic translation framework, (continued)
- [Qemu-devel] [PULL 14/32] target/i386: [tcg] Port to generic translation framework, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 13/32] target/i386: [tcg] Port to disas_log, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 18/32] target/arm: [tcg] Port to tb_start, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 20/32] target/arm: [tcg, a64] Port to insn_start, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 16/32] target/arm: [tcg] Port to init_disas_context, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 19/32] target/arm: [tcg] Port to insn_start, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 25/32] target/arm: [tcg,a64] Port to tb_stop, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 15/32] target/arm: [tcg] Port to DisasContextBase, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 24/32] target/arm: [tcg] Port to tb_stop, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 26/32] target/arm: [tcg] Port to disas_log, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 17/32] target/arm: [tcg, a64] Port to init_disas_context,
Richard Henderson <=
- [Qemu-devel] [PULL 22/32] target/arm: [tcg] Port to translate_insn, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 21/32] target/arm: [tcg, a64] Port to breakpoint_check, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 28/32] target/arm: [tcg] Port to generic translation framework, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 23/32] target/arm: [tcg, a64] Port to translate_insn, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 29/32] target/arm: [a64] Move page and ss checks to init_disas_context, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 27/32] target/arm: [tcg,a64] Port to disas_log, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 30/32] target/arm: Move ss check to init_disas_context, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 32/32] target/arm: Perform per-insn cross-page check only for Thumb, Richard Henderson, 2017/09/06