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[Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR |
Date: |
Mon, 4 Sep 2017 13:25:41 +0100 |
For M profile the XPSR is a similar but not identical format to the
A profile CPSR/SPSR. (For instance the Thumb bit is in a different
place.) For guest accesses we make the M profile code go through
xpsr_read() and xpsr_write() which handle the different layout.
However for migration we use cpsr_read() and cpsr_write() to
marshal state into and out of the migration data stream. This
is pretty confusing and works more by luck than anything else.
Make M profile migration use xpsr_read() and xpsr_write() instead.
The most complicated part of this is handling the possibility
that the migration source is an older QEMU which hands us a
CPSR format value; helpfully we can always tell the two apart.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/machine.c | 49 ++++++++++++++++++++++++++++++++++---------------
1 file changed, 34 insertions(+), 15 deletions(-)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 2fb4b762..3193b00 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -217,21 +217,37 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t
size,
uint32_t val = qemu_get_be32(f);
if (arm_feature(env, ARM_FEATURE_M)) {
- /* If the I or F bits are set then this is a migration from
- * an old QEMU which still stored the M profile FAULTMASK
- * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask
- * accordingly, and then clear the bits so they don't confuse
- * cpsr_write(). For a new QEMU, the bits here will always be
- * clear, and the data is transferred using the
- * vmstate_m_faultmask_primask subsection.
- */
- if (val & CPSR_F) {
- env->v7m.faultmask = 1;
- }
- if (val & CPSR_I) {
- env->v7m.primask = 1;
+ if (val & XPSR_EXCP) {
+ /* This is a CPSR format value from an older QEMU. (We can tell
+ * because values transferred in XPSR format always have zero
+ * for the EXCP field, and CPSR format will always have bit 4
+ * set in CPSR_M.) Rearrange it into XPSR format. The significant
+ * differences are that the T bit is not in the same place, the
+ * primask/faultmask info may be in the CPSR I and F bits, and
+ * we do not want the mode bits.
+ */
+ uint32_t newval = val;
+
+ newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);
+ if (val & CPSR_T) {
+ newval |= XPSR_T;
+ }
+ /* If the I or F bits are set then this is a migration from
+ * an old QEMU which still stored the M profile FAULTMASK
+ * and PRIMASK in env->daif. For a new QEMU, the data is
+ * transferred using the vmstate_m_faultmask_primask subsection.
+ */
+ if (val & CPSR_F) {
+ env->v7m.faultmask = 1;
+ }
+ if (val & CPSR_I) {
+ env->v7m.primask = 1;
+ }
+ val = newval;
}
- val &= ~(CPSR_F | CPSR_I);
+ /* Ignore the low bits, they are handled by vmstate_m. */
+ xpsr_write(env, val, ~XPSR_EXCP);
+ return 0;
}
env->aarch64 = ((val & PSTATE_nRW) == 0);
@@ -252,7 +268,10 @@ static int put_cpsr(QEMUFile *f, void *opaque, size_t size,
CPUARMState *env = &cpu->env;
uint32_t val;
- if (is_a64(env)) {
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */
+ val = xpsr_read(env) & ~XPSR_EXCP;
+ } else if (is_a64(env)) {
val = pstate_read(env);
} else {
val = cpsr_read(env);
--
2.7.4
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 05/36] hw/intc/armv7m_nvic.c: Remove out of date comment, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 04/36] target/arm: Tighten up Thumb decode where new v8M insns will be, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in get_phys_addr(), Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 06/36] target/arm: Remove incorrect comment about MPU_CTRL, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 07/36] target/arm: Fix outdated comment about exception exit, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 01/36] target/arm: Use MMUAccessType enum rather than int, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 02/36] target/arm: Don't trap WFI/WFE for M profile, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 09/36] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR,
Peter Maydell <=
- [Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode(), Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 18/36] hw/arm: use defined type name instead of hard-coded string, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 15/36] nvic: Implement "user accesses BusFault" SCS region behaviour, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 14/36] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 16/36] loader: Handle ELF files with overlapping zero-initialized data, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 22/36] target/arm/kvm: pmu: improve error handling, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 17/36] loader: Ignore zero-sized ELF segments, Peter Maydell, 2017/09/04